Tessent Silicon Lifecycle Solutions

WEBINAR - LAST CALL! Don't miss this opportunity to gain an expert introduction to Tessent UltraSight-V, the end-to-end debug & trace solution for RISC-V based SoCs from Siemens EDA. Presented by Francisca Tan, Product Management Lead and Mike Sharp, Product Engineer, Tessent Embedded Analytics, the webinar will provide a technical insight into UltraSight-V, a solution that consists of embedded IPs and software that integrate with industry-standard tools. The webinar will detail how the integration of UltraSight-V’s on-chip IP modules and host software can empower engineers to efficiently diagnose the root causes of unexpected behavior and underperformance. UltraSight-V is designed to meet the official RISC-V trace specification and to support embedded software engineers to develop high-performance embedded software. To learn more, register today. Europe Webinar | 10am BST | Registration: https://sie.ag/5qaRc4 USA Webinar | 9am PDT | Registration: https://sie.ag/4FSzXH #TessentUltraSightV #UltraSightV #TessentEmbeddedAnalytics #SiemensEDA

The Tessent Silicon Lifecycle Solutions team is proud to invite our customers and partners to explore the latest trends in EDA at this year's Siemens EDA User2User Conferences in Europe and North America. This remains an exciting opportunity to join your fellow DFT professionals for exclusive introductions to the latest technology innovations, industry keynotes, expert presentations, networking and much more from Siemens EDA. Plus don't miss the dedicated Tessent track, covering Design for Test and incorporating key customer technical presentations. Follow the links below for more details and the full agenda. Learn more and reserve your free customer place today. U2U Europe - 13th May: https://sie.ag/21CkBN U2U North America - 20 May: https://sie.ag/6mmHTJ #U2U2024 #Tessent #DFTMarketleader #semiconductors #SiemensEDA #DFT

Finally going home after an extensed stay in the US following the fire at Heathrow last week. Working with safety on a daily basis, this whole experience has really highlighted the difference to me between failure detection and mitigation, in this case the airport being shut down due to the substation failure and health monitoring, where prehaps preventative action could have been taken on an aging piece of equipment that was obviously reaching the end of its life. I appreciate we are talking completly different scales between electrical substations and Semiconductors, but depending on the application the impact could be similar.

Learn how Tessent In-System Test (IST) enables high-quality deterministic test patterns and how it enhances Tessent Streaming Scan Network (SSN) in this interview with Lee Harrison, Director of Product Marketing, Siemens EDA. In-system deterministic test enables test patterns to be changed as new defects and fault models emerge or as test content needs change. Lee explains how Tessent IST complements Tessent SSN and enhances its ability to be used in an in-system, in-field environment, thus extending the advanced technology that Tessent SSN provides. Watch now. https://sie.ag/3U8ctE #DFT #TessentInSystemTest #TessentStreamingScanNetwork #TessentSSN #Semiconductors #EDA

I am pleased to share that our recent paper On Near-Maximum-Length Galois Nonlinear Feedback Shift Registers has been published in the April issue of IEEE TCAD. https://lnkd.in/g6EyfbW2 Here are the key points: ·?NLFSRs have strong cryptographic properties and are important security primitives for applications like hardware roots of trust, stream ciphers, and cryptographic key management. ·?This paper presents two new sets of Galois NLFSRs - one with maximum length (period of 2^n - 1) and another with near-maximum prime periods. ·?It provides comprehensive tables listing the architectural details and metrics for the identified NLFSRs, which can be useful for designers working on security-critical systems. ·?The paper discusses how the near-maximum-length NLFSRs can be used to construct larger nonlinear finite state machines by combining multiple NLFSRs with relatively prime periods. This allows building complex cryptographic primitives without relying on the elusive maximum-length NLFSRs.

In this Siemens EDA Diamond presentation by NVIDIA, Vishal Agarwal, Senior Director, H/W Engineering, explains how, as modern AI systems are very large and complex designs, NVIDIA built a new test architecture to meet its testability challenges using Tessent Streaming Scan Network (SSN) technology. Vishal also provides an insight into NVIDIA's vision for solving upcoming challenges for this once-in-a-decade technology shift. To learn more, watch Vishal's full presentation which was delivered recently at the International Test Conference in San Diego. https://sie.ag/6CtsWn #TessentSSN #TessentStreamingScanNetwork #TessentInSystemTest #IC #IntegratedCircuitDesign #DFTIndustryleader #DFT #SiemensEDA

Did you know that by leveraging Tessent’s high resolution chain diagnosis technology, organizations can improve yield by by finding more systematic defects and improving resolution by up to 80%. In this interview, Jayant D'Souza, Senior Product Manager, Tessent, explains how and answers key questions including: - What's driving the need for resolution improvements? - How are we resolving better? - What is the value of yield in the chiplet economy? - What have customers seen to date by using this technology? To learn more, watch Jayant's full Subject Matter Expert interview now. https://sie.ag/6vbNMf #HiResChain #YieldLearning #Scanchaindiagnosis #DFT #semiconductors

As the RISC-V ecosystem continues to grow, the need for robust verification and debug solutions remains increasingly important. However, the time, effort and cost of debugging and optimizing software running on current multi-core SoCs also continues to escalate as design complexity increases. Consequently, more efficient methods to debug, iterate, and scale such systems are required to identify hardware and real-time software issues in these systems. Tessent UltraSight-V from Siemens EDA, is designed to address these challenges and to help streamline the RISC-V design process. A new, comprehensive, end-to-end debug & trace solution for RISC-V based SoCs, Tessent UltraSight-V is specifically designed to support and enable embedded software engineers to develop high-performance embedded software, whilst maintaining compliance with the official RISC-V trace specification. To learn more, register today for one of the live Tessent webinar sessions on Tue 1 April. Europe Webinar | 10am BST | Registration: https://sie.ag/6DJDpH USA Webinar | 9am PDT | Registration: https://sie.ag/6kirsZ #TessentUltraSightV #UltraSightV #RISCV #TessentEmbeddedAnalytics

Watch as Marc Hutner, Director of Product Management for Tessent Silicon Learning, provides his expert insight into the future of SLM. Marc explains how DFT is no longer used just for test but is instead becoming a functional subsystem for products. In his interview, he describes how SLM is helping to extend the lifetime of a product by understanding the health of the complete system. Key areas covered include: - What is SLM and how does it relate to Tessent? - How do Tessent solutions apply to SLM? - What problem does SLM EA solve for customers? - What are the important themes going forward? Watch Marc's full interview now to learn more. https://sie.ag/6nrMiS #SiliconLifecycleManagement #Tessent #YieldLearning #DFT #EDA #3DIC #semiconductors

In this presentation recording, Anurag Jindal, Head of DFX group at Ericsson, provides a unique insight into "Faster & more effective flow enabled by an integrated platform" at Ericsson. Recorded at last year's International Test Conference North America, you can watch Anurag's full Siemens Diamond event presentation here. https://sie.ag/7TegP8 #TessentSSN #TessentStreamingScanNetwork #TessentInSystemTest #3DIC #DFTIndustryleader #DFT #SiemensEDA