Tessent Silicon Lifecycle Solutions

In this Siemens EDA Diamond presentation by NVIDIA, Vishal Agarwal, Senior Director, H/W Engineering, explains how, as modern AI systems are very large and complex designs, NVIDIA built a new test architecture to meet its testability challenges using Tessent Streaming Scan Network (SSN) technology. Vishal also provides an insight into NVIDIA's vision for solving upcoming challenges for this once-in-a-decade technology shift. To learn more, watch Vishal's full presentation which was delivered recently at the International Test Conference in San Diego. https://sie.ag/6CtsWn #TessentSSN #TessentStreamingScanNetwork #TessentInSystemTest #IC #IntegratedCircuitDesign #DFTIndustryleader #DFT #SiemensEDA

Did you know that by leveraging Tessent’s high resolution chain diagnosis technology, organizations can improve yield by by finding more systematic defects and improving resolution by up to 80%. In this interview, Jayant D'Souza, Senior Product Manager, Tessent, explains how and answers key questions including: - What's driving the need for resolution improvements? - How are we resolving better? - What is the value of yield in the chiplet economy? - What have customers seen to date by using this technology? To learn more, watch Jayant's full Subject Matter Expert interview now. https://sie.ag/6vbNMf #HiResChain #YieldLearning #Scanchaindiagnosis #DFT #semiconductors

As the RISC-V ecosystem continues to grow, the need for robust verification and debug solutions remains increasingly important. However, the time, effort and cost of debugging and optimizing software running on current multi-core SoCs also continues to escalate as design complexity increases. Consequently, more efficient methods to debug, iterate, and scale such systems are required to identify hardware and real-time software issues in these systems. Tessent UltraSight-V from Siemens EDA, is designed to address these challenges and to help streamline the RISC-V design process. A new, comprehensive, end-to-end debug & trace solution for RISC-V based SoCs, Tessent UltraSight-V is specifically designed to support and enable embedded software engineers to develop high-performance embedded software, whilst maintaining compliance with the official RISC-V trace specification. To learn more, register today for one of the live Tessent webinar sessions on Tue 1 April. Europe Webinar | 10am BST | Registration: https://sie.ag/6DJDpH USA Webinar | 9am PDT | Registration: https://sie.ag/6kirsZ #TessentUltraSightV #UltraSightV #RISCV #TessentEmbeddedAnalytics

Watch as Marc Hutner, Director of Product Management for Tessent Silicon Learning, provides his expert insight into the future of SLM. Marc explains how DFT is no longer used just for test but is instead becoming a functional subsystem for products. In his interview, he describes how SLM is helping to extend the lifetime of a product by understanding the health of the complete system. Key areas covered include: - What is SLM and how does it relate to Tessent? - How do Tessent solutions apply to SLM? - What problem does SLM EA solve for customers? - What are the important themes going forward? Watch Marc's full interview now to learn more. https://sie.ag/6nrMiS #SiliconLifecycleManagement #Tessent #YieldLearning #DFT #EDA #3DIC #semiconductors

In this presentation recording, Anurag Jindal, Head of DFX group at Ericsson, provides a unique insight into "Faster & more effective flow enabled by an integrated platform" at Ericsson. Recorded at last year's International Test Conference North America, you can watch Anurag's full Siemens Diamond event presentation here. https://sie.ag/7TegP8 #TessentSSN #TessentStreamingScanNetwork #TessentInSystemTest #3DIC #DFTIndustryleader #DFT #SiemensEDA

Discover Scan diagnosis – an essential component for yield and failure analysis in this live webinar presented by Jayant D'Souza, Technical Product Director for yield learning, Tessent. Scan diagnosis has been used for yield analysis and to drive failure analysis for several years over multiple technology nodes. As process technology becomes more complex, especially with the advent of backside power delivery (BPD), scan diagnosis is becoming increasingly important for today's yield and failure analysis. In this webinar, Jayant will introduce the basics of scan diagnosis and illustrate how some of the latest algorithms can be leveraged to reduce FA cycle time and yield analysis by up to 90%. Don't miss learning more about this essential topic, register for this free webinar today. https://sie.ag/29hYLS #HiResChain #YieldLearning #Scanchaindiagnosis #chiplets #DFT #Tessent #DFTMarketLeader #SiemensEDA #3DIC #semiconductors

It's a wrap at this week's Embedded World Europe in Nuremberg after a very busy and knowledge sharing few days. It was a fantastic event for Siemens EDA and the Tessent Embedded Analytics team and we would like to say a big thank you to everybody that joined us in the #RISCV pavilion and expressed interest in the new Tessent UltraSIght-V and wider range of RISC-V solutions that help organizations to manage the risk of adopting RISC-V architecture. We look forward to meeting you all again next year and would like to leave you with a quick recap of this year's event with these images below. To learn more about Tessent Embedded Analytics and our range of industry leading RISC-V solutions, visit: https://sie.ag/4MxYoj #EW2025 #Tessent #UltraSightV #SoC #Debug #TessentESDK #EmbeddedSDK #SiemensEDA

Discover Tessent UltraSight-V, a comprehensive debug and trace solution for RISC-V processors that combines embedded IP and software to enable efficient debugging and tracing, in this blog post from Siemens EDA. The blog explains the multiple benefits of UltraSight-V for organizations, which include: - A complete solution for RISC-V debug and trace - Designed to meet the official RISC-V trace specification - An end-to-end solution consisting of embedded IP and software - Provides comprehensive and efficient debugging and trace capabilities - Integrates with industry-standard tools - Supports & empowers embedded software engineers to develop high-performance embedded software Learn more about how to accelerate RISC-V development with Tessent UltraSight-V, by reading the full blog today. https://sie.ag/4e3MzV Alternatively, you can also learn more about how UltraSight-V can empower embedded software engineers to develop high-performance embedded software by registering for our Live webinar sessions on Tue, 1 April. Europe Webinar | 10am BST | Registration: https://sie.ag/6fkYMc USA Webinar | 9am PDT | Registration: https://sie.ag/68uLtn #TessentUltraSightV #UltraSightV #TessentEmbeddedAnalytics #RISCVEtrace #Tessent

Still time to meet up at Embedded world & learn more about how Tessent Embedded Analytics may help you reduce debug/development time for your SoC project... come visit us in Hall 5 119 #RISC-V #SoC #debug #Trace #Siemens #Embeddedworld2025

There was a real buzz of anticipation in the air as Embedded World Europe 2025, in Nuremberg, opened its doors to thousands of delegates on its first day. Located on the RISC-V pavilion, the Tessent Embedded Analytics team from Siemens EDA, remained extremely busy introducing Tessent UltraSight-V and the complete range of industry leading RISC-V solutions. Check out the days proceedings in the images below. If you're at the show this week, we highly recommend that you don't miss the expert Tessent presentation by Devan Sharma, Account Technology Manager for Europe & India on Wed, 12 Apr, at 1.15pm, (RISC-V pavilion, Hall 5, #5-119). Devan will be providing an introduction to Tessent UltraSight-V, a new end-to-end RISC-V debug and trace solution that enables system-wide, real time, debug and post-deployment analytics for complex SoCs, and which is designed to meet the official RISC-V trace specification. We look forward to meeting you at the show. To learn more about Tessent RISC-V solutions, visit: https://sie.ag/5sWQmS #RISCVSummit #RISCVeverywhere #TessentESDK #EmbeddedSDK #SiemensEDA #Catapult Lathif Sharieff, Mike Sharp, Russell Klein (Catapult), Aaron Jin