Solido Custom IC Solutions (Siemens EDA)

Missed the live event? Register for TSMC OIP Ecosystem Forum On-Demand!? Be sure to watch the Infineon Technologies/Siemens EDA (Siemens Digital Industries Software) joint presentation entitled ? “A library-focused approach to standard cell IP evaluation and selection for automotive ICs” This presentation describes a combined approach using Siemens #Solido Library Profiler and Solido Generator tools that achieves crucial PPA analysis for Infineon’s IP selection needs. The methodology provides fast and correct alignment of differently structured and named cells, pins, arcs, and other library information purely using .lib data from diversely sourced libraries. This has enabled #infineon to make educated decisions on #IP selection between TSMC 28eF 7-track and 13-track, where the 7-track was found to be most suitable for projects with #low #power requirements, and the 13-track for those with high performance requirements. As a global leader in the automotive semiconductor space, Infineon’s work on automotive cores requires choosing the appropriate digital standard cell library for IC design optimization based on power, performance, and area (PPA). This study presents Infineon’s utility of Siemens Solido Library Profiler and Solido Generator for quick and efficient PPA analysis to determine the ideal library for production between TSMC 28eF 7-track and TSMC 28eF 13-track libraries. Standard cell libraries are fundamental in integrated circuit design, as they lay the foundation for enabling efficient, reliable, and scalable IP. Standard cell libraries utilize universal Liberty (.lib) data formatting and provide comprehensive information of a library to describe timing, power, and area characteristics of cells. Choosing the correct standard cell library is essential to optimize for PPA of the IP and will have lasting impact on the final product. This selection process can often be difficult and time consuming due to inherent differences of IP from various sources and/or tech nodes such as differences in cell naming conventions and data structure. Decision on IP usage based on PPA analysis traditionally is also a daunting and time-consuming task, often requiring design teams to synthesize multiple reference designs and numerous iterative runs through synthesis, static timing analysis (STA), and place and route (P&R). Register here - ?https://lnkd.in/ekUgykvE

Hi All, ? Custom IC (CIC) – Solido??IP Validation?team is looking to hire??2???“Software Testing & Quality Assurance Engineers”??to join our team in?Cairo, Egypt?(contractor positions). ? Solido??IP Validation Suite provides the fastest, most comprehensive silicon IP quality assurance for IC design.?It integrates with industry-leading solutions to provide complete, seamless IP QA from design tapeout start to finish, and ensures a high-quality IP release at every iteration.??Solido? IP Validation Suite consists of Solido? Crosscheck and Solido? IPdelta, offering in-view and cross-view IP QA, as well as version-to-version IP QA, respectively. Used together, these solutions create a robust IP QA flow, accelerating IP production cycles and helping to maintain a high level of IP quality with each iteration. ? We are targeting highly motivated members who will be part of the QA team who aims to reach a high-level quality for the products. The candidates should be self-motivated, attentive to details and able to work independently. ? Job Description: Develop and execute test plans for each release in coordination with development and marketing teams. Work closely with the development teams to qualify Solido IP Validation products. Identify, analyze, and troubleshoot product issues and report them effectively. Analyze defects reported by customers and automate their test cases. Ensure compliance with quality standards while validating the various products by considering different quality attributes (FURPS). Evaluate test coverage and propose enhancements. Design innovative scenarios targeting different customer use models to identify issues and offer suggestions for improvement. Job Qualifications: B.Sc/M.Sc in Electronics Engineering with minimum grade of very good or equivalent GPA. 0-3 years of experience. Good knowledge of Analog IC and Digital ASIC design flows. Fundamental knowledge of Digital ASIC design including experience with the design flow from specification to verification. Good understanding of digital verification methodologies is a plus. Knowledge of VHDL, Verilog, Liberty and LEF files, Spice netlists is a plus. Python, Shell Scripting and UNIX knowledge is a plus. Basic knowledge of QA methodologies and in development tools (version management, defect management, test coverage) is highly desirable. Strong communication skills: Ability to work effectively in a team environment, clearly document testing results and efficiently communicate with QA members, developers, and field engineers. Fluent in English with good written and verbal communication skills. ? If interested or know good candidates, please send?the CV to?[email protected]??with the subject?“Solido IP Validation – QA Position”

NEWS Flash -->> Siemens strengthens leadership in industrial software and AI with acquisition of Altair Engineering > Acquisition of Altair Engineering Inc., a global leader in computational science and artificial intelligence software, strengthens Siemens’ position as a leading technology company > ?? Creates the world's most complete AI-powered design and simulation portfolio > Siemens expects to achieve significant cost and revenue synergies ? Read press release here -> https://lnkd.in/gtuvCFtk

Join Siemens EDA (Siemens Digital Industries Software) at the Tower Semiconductor TGS event on 11/20 in Santa Clara, CA. https://lnkd.in/dXGTMrvB

Thank you Yuling Lin for sharing this post and for representing Siemens EDA (Siemens Digital Industries Software) Custom IC Solutions at the TSMC OIP forum in Tokyo!

NEWS Flash -->> Siemens extends collaboration with TSMC to advance integrated circuit and systems design Siemens EDA (Siemens Digital Industries Software) announced it has extended its longstanding collaboration with TSMC through multiple new development projects, product certifications and innovative technology enablement for the foundry’s newest process technologies. Mutual customers can develop highly differentiated end-products with confidence using Siemens’ best-in-class EDA solutions together with TSMC’s industry-leading silicon process and advanced packaging technologies. "Strengthening our ongoing alliance with Open Innovation Platform? (OIP) ecosystem partners like Siemens keeps us at the forefront in accelerating advancements in 3D IC design for AI innovation," said Dan Kochpatcharin, Head of Ecosystem and Alliance Management Division at TSMC. "Our longtime collaboration with Siemens allows our mutual customers to fully harness the power, performance, and efficiency of TSMC's cutting-edge technologies." Siemens and TSMC have collaborated to certify parts of Siemens’ Solido Simulation Suite software for analog, mixed-signal, RF and memory designs, with the recent certification of Siemens’ Solido SPICE and Analog FastSPICE (AFS) tools for TSMC’s N2 and N2P processes. Further, as part of the custom design reference flow (CDRF) for TSMC’s N2 process, Siemens’ AFS tool now supports TSMC’s Reliability Aware Simulation technology, which addresses IC aging and real-time self-heating effects, among other advanced reliability features. The CDRF for TSMC’s N2 technology also integrates Siemens’ Solido Design Environment software for advanced variation-aware verification. “Siemens EDA’s extensive and successful collaboration with TSMC enables advanced solution certifications for the latest process technologies required by our mutual customers,” said Mike Ellow, CEO, Silicon Systems, Siemens Digital Industries Software. "By integrating Siemens' top-tier IC design tools with TSMC's state-of-the-art processes and advanced packaging technologies, we empower our shared customers to achieve groundbreaking and transformative innovations." read full press release here>> https://lnkd.in/ejbPsx74

>> Paper - Advancing automotive functional safety through analog & mixed-signal fault simulation ?? The #automotive industry is undergoing a major transformation, driven by the rise of electric vehicles, ADAS, connected cars, and autonomous vehicles. Due to the safety-critical nature of automotive applications, the reliability and tolerance to faults in semiconductor designs becomes paramount. Modern cars have an increasing number of analog sensors to improve performance, efficiency, and driver assistance. Most modern cars are also equipped with internet connectivity and other advanced technologies. This connectivity in cars provides real-time navigation updates, traffic information, remote vehicle control, and emergency services, enhancing convenience and safety. In the future, these technologies will allow connected cars to communicate with each other, with infrastructure, and with the driver – all further improving passenger safety. The next phase of innovation is self-driving. Autonomous vehicles are vehicles that can drive themselves without human intervention. This technology is still in its early stages of development, but it has the potential to revolutionize the automotive industry. Autonomous vehicles could make transportation safer, more efficient, and more accessible. While self-driving technology continues to advance, autonomous features like adaptive cruise control and lane-keeping assist are finding their place in traditional human-controlled cars. Semiconductor chips fuel the innovation, safety, and comfort that propel modern vehicles into the future of transportation. Automotive systems are responsible for the safety of drivers, passengers, pedestrians, and other road users. Faulty semiconductor components can lead to critical failures in systems like airbags, brakes, steering, and more, potentially causing accidents, injuries, or fatalities. Vehicles operate in a wide range of environments, including extreme temperatures, humidity, vibrations, and electromagnetic interference. Semiconductors must be designed to withstand these conditions without performance degradation or failure. Validating semiconductor components for automotive applications is a complex process that involves extensive testing, simulation, and verification. Ensuring reliability and fault tolerance requires rigorous testing across various conditions and scenarios. Read full paper to learn more about how you can harness the power of Siemens EDA solutions to address the challenges associated with analog and mixed-signal fault simulation. https://lnkd.in/e85FPUfq

Attending TSMC OIP Ecosystem Forum, November 13th in Beijing, China? ?? Don’t miss the joint Microsoft / Siemens EDA (Siemens Digital Industries Software) live session at 11:35 in the Mobile, IoT & Automotive Track . The session, entitled ‘A comprehensive IP validation methodology for Microsoft’s AI and high-performance compute chips (Microsoft/Siemens EDA)’ Explores the various challenges in IP production and integration flows. It also explores how Microsoft addresses these challenges using the Siemens’ Solido IP Validation Suite for in-view, cross-view, and version-to-version IP validation. By employing the Solido IP Validation Suite, Microsoft ensures the production and integration of high-quality IPs, leading to more reliable and efficient AI and high-performance compute chips. This results in better performance, enhanced IP production milestones, and a competitive edge in the rapidly evolving semiconductor industry. The increasing complexity of AI and high-performance compute chips, highlighted by advanced node technologies like TSMC's N5, N3, N2, requires sophisticated design approaches to manage high transistor counts, heterogeneous integration, and demanding power requirements. Modern chips integrate various processing units, such as CPUs, GPUs, and AI accelerators, and need high-bandwidth memory and advanced interconnects to handle massive data flows efficiently. To address these challenges, modularization using design IPs has become essential. Design IPs reduce design time and cost by providing pre-designed, pre-verified components, ensuring proven quality and reliability. This allows designers to focus on unique, differentiating aspects of their chips while maintaining scalability and flexibility. Moreover, industry-standard IPs ensure ecosystem compatibility and streamline integration, facilitating the creation of innovative and competitive AI and high-performance compute chips. The use of design IPs also comes with challenges in production and integration into complex SoCs. For example, inconsistencies can arise across different views and formats, such as Verilog, LEF, DEF, GDS, .libs, etc. These inconsistencies can pass through the entire design flow undetected, leading to incorrect optimization of the design, and result in suboptimal power, performance, and area (PPA) metrics or, in worse cases, necessitate silicon re-spins. Ensuring alignment and consistency across these various views and formats is crucial to avoid these challenges and achieve quality IP design. https://lnkd.in/eVqQX4iN

We have signed an agreement to acquire Altair, a leading provider of #software in the industrial #simulation and analysis market. With this acquisition we strengthen our position as a leading technology company and the leader in industrial software and #AI.

>> PAPER - Verifying SRAM yield inclusive of rare and random defects leveraging Solido Design Environment’s AI-powered methodology GlobalFoundries 12nm technology has been highly successful in the worldwide semiconductor market. A popular product offered on this technology platform is SRAM (Static Random Access Memory). Various kinds of SRAM bitcells catering to different applications and power/performance/density specifications are offered. However, the constant march towards ever smaller bitcell footprints and the quest for higher performance continues. Large disparities were observed between wafer level SRAM Access Disturb related bit-fails as measured on silicon wafers and the number of such bit-fails as predicted by intrinsic device variability alone. Root cause investigations pointed to a rare but random defect lowering threshold voltage of the NFET devices of the SRAM bit-cell. This white paper presents a novel method to enable the inclusion of such rare and random defects into yield prediction frameworks. Solido Design Environment (Solido DE) has been utilized to demonstrate that the bit-fail counts predicted using the proposed novel method match closely with the silicon data. https://lnkd.in/eSj-ggeP