Your S21 Isn’t 0 dB at Low Frequency. Are You Okay with That?
Chun-Ting "Tim" Wang Lee, PhD
SI Application Scientist at Keysight Technologies
We are familiar with S21 of a point-to-point passive interconnect. It tells us the loss of the interconnect across frequencies. In the point-to-point case, we expect the S21 to be close to 0 dB at low frequency. Because when the frequency is low, the wavelength is so large that there are no amplitude and phase variations along the physical length. The result is the entire interconnect looking like a transparent thru. S21 is 0 dB. Everything is transmitted.??
Things get tricky when one is looking at a one-to-many, multi-drop connection. The command lines and address lines of a memory system are examples of this one-to-many, multi-drop connection. Illustrated in the figure below, one can see the 1 transmitter at the DIMM register, and the 10 receivers at the DRAMs.
This one-to-many connection challenged my Signal Integrity (SI) intuition. I was SO sure that the S21 must be close to 0 dB at low frequency…?
To recalibrate my intuition, I went back to the basics. I drew up the schematic of an address line, applied simple assumptions and performed circuit analysis to get the S21. The result is in the figure below. Based on my analysis, I should expect the low frequency S21 of this address line to be around -15 dB.
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The address line was then simulated in Keysight SIPro. As shown below, the simulated S21 at low frequency is consistent with my recalibrated expectation.?
This consistent result renews my SI intuition. In the process, I also trust-but-verify my EM solver. I am even more confident that SIPro is good for simulating memory applications.???
From this experience, I realize that although the knowledge for SI basics is readily available, rule of thumbs and expectations are usually based on point-to-point connections. If you want to recalibrate your SI intuition, and update your SI knowledge to the simulation and measurements of memory interfaces, make sure to join my colleagues at DesignCon Keysight Educational Forum (KEF).
Quick Guide to Recalibrate Your Signal Integrity Intuition for Memory Interfaces
Location: 210E?Room
Wednesday, August 18, 8:30 am – 9:10 am
IPC Certified PCB Designer at TUSAS Malaysia
3 年I have the same simulation result with SI Pro. Now I know why. Thanks for your explanations ?? .
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3 年Great article Tim. I love your thoughts on this. I would add that if you're looking at signals on a DIMM, it will depend on what nets you're looking at. For CAC nets (non point-to-point) the loss could be -10dB or -15dB depending on the number of DRAM used in the fly-by topology. Which you discussed. For DQ nets (or point-to-point nets) on a DIMM there is a series resistor that will affect your loss seen at DC.
Staff System Electrical Engineer (High Speed Digital Design Focus) at ZT Systems
3 年Chun-Ting "Tim" Wang Lee, PhD Nicely explained. This surely helps me recalibrate my intuition.