Which Memory IP Should I Choose?
Ronen Laviv
EDA and Cloud consultant | Driving digital transformation | Mid size and Enterprise companies | Business development for Greenfield Companies | Nurturing growth with established customers | AI Transformation
If you're about to start a design or just want to better understand differences between available memories out there, this article might be for you. We will review the types of memory IP available today and discuss when it makes sense to use each of them. We will also touch on how to make sure you're comparing apples to apples when choosing between the various vendors.
Market Analysis
Let’s start with a market analysis. As of 2020, the majority of existing designs today are using LP/DDR4. This is derived from dimms availability and cost.
Looking forward we are seeing designs starting with LP/DDR4 but there's a growing demand for LP/DDR5, GDDR6, and HBM.
A Brief Review of the Memories
HBM / HBM2 / HBM2E:
High-Bandwidth Memory (HBM) is a very efficient memory type: 1,024 I/Os and 1TB/s of system memory bandwidth with 256GB/s. With those rates, the HBM is serving high-speed networking, servers, AI and gaming applications. It's mainly a bandwidth solution.
HBM requires more skills to design and manufacture. In the HBM case, there are 1024+ signals going between the main SoC and the memory. Old-school package methodology is not able to connect the two. So instead there's another layer of silicon, called interposer, that is used to connect the SoC and the external memory. This also means that the HBM memory and the SoC must be packaged together.
There are a few aspects to consider when using an HBM:
- Design and packaging complexity
- Yield and testability challenges
- Cost of interposer, design, and more complex/expensive packaging compared to DDR/GDDR family that does not require interposer
- Cost of the memory itself—HBM must be purchased in advance and packaged as inventory, which means that the SoC vendor invests in memory and becomes a memory distributor
GDDR6
The Graphic Dual Data Rate type 6 (GDDR6) has data rate of up to 16Gps (though you may find leaks on companies claiming they go support 20Gbps. Capacity wise, up to 16GB (as of the time of writing, with leaks of 20GB). Compared to the HBM, it is about 1.5X-1.75X in size and 3.5X-4.5X in power, but it doesn't require interposer and is much easier to handle.
Traditionally, the target market for GDDR6 was graphics, but it has expanded to AI. In addition, GDDR6 could be applied in automotive applications, unlike the HBM, which is not a good fit due to packaging complexity.
DDR5
DDR5 is more of a capacity solution. Target devices are high-speed networking, storage products, and servers. As for performance, first products will target 4800Mbs, and in a year, we should expect an increase in the performance bin. DDR5 can:
· Deliver larger dies while managing timing challenges
· Solve retention time problem (with on-die ECC)
· Provide same speed DRAM core with higher speed I/O
· Increase 1 speed grade every 12-18 months
LPDDR5
LPDDR5 will add more speed at less energy per bit compared to DDR5. This type of memory targets AI technology, autonomous driving, 5G networks, advanced display options, and the mobile market. LPDDR5 speed grades reach 5500Mbs and the near future might carry improvement in performance for these, as well, with the transfer rate increased to 6400Mbs. This memory is lowest in cost (HBM is the costliest, followed by GDDR6, then LPDDR5).
DDR4/LPDDR4/4X
DDR4 is more than 10 years old, and most customers are looking into transitioning to DDR5. Nevertheless, most IP today supports both DDR5 and DDR4 using a combo solution.
As LP/DDR4 is cheaper than the standalone LP/DDR5 solution, we still find consumer applications using it. Compared to LP/DDR5, the data rate is slower and capacity is smaller.
LPDDR4X is still widely used as it is running at same data rate but uses less than half of the power per bit compared to LPDDR4.
For LPDDR4/4X, the maximum data rate is 4266Mbs (4.2Gbs) and the frequency is always half (double data rate). It is widely used in automotive applications.
Matching Applications to DRAM Types
If you're looking at cost and bandwidth, you should start with LPDDR5, which today is at 5500Mbs (and soon will be even faster). The next fastest choice is GDDR6, today 16Gbs (and soon even faster). Eventually, if you need more bandwidth, HBM2E is at 3.6Gbs although it requires more signals in parallel to get the largest bandwidth.
As of today, HBM2 can handle the largest bandwidth. To match that with other types of memories, you’ll need to place multiple instances of other memories.
Apples to apples comparison when choosing a PHY
When designing a chip, one should take a careful look at the power, performance, and area (PPA), latency, error correction, and utilization. Those are usually easy to compare.
What I noticed and wanted to bring to your attention is the quoting of the memory size by different vendors. Looking at the actual design of the memory PHY, some vendors report the slice area in red, while other vendors, such as Cadence, refer to the overall area of the actual PHY.
Cadence publishes the green rectangle. It is the final size of the PHY and includes hard data slices, hard CA slices, hard clocks, generation blocks, PHY independent training logic, all PHY registers, hard wide (I/O) to narrow (DFI) clocks, interconnects, and logic, I/Os, PLLs, DLLs, and decaps required to run the more advanced frequencies.
Other vendors might publish the size of the macros, the red area, which might NOT contain PHY training logic, PLLs, required decaps outside hard data and CA slices, hard wide (I/O) to narrow (DFI) interconnects, and logic.
So pay attention to that point when you benchmark the different vendors, as you might be looking at an orange rather than an apple.
To Sum Up
We reviewed the basics of today’s memory interfaces. All of them can be verified with verification IP models. Hopefully you now have a better understanding of the differences between them. If I missed anything you are interested in, please don't be shy, drop me a comment below or send a PM.
DRAM circuit design
4 年Great overview! To add some useless opinions (commonly we say adding legs to the snake), using LP5 costs more than DDR5, due to the channel condition. LP series are designed under the minor agreement of using the point to point class channels like a bonding wire. DDR series are ready to be used under harsh channel conditions like multi-ranks, multi-dies, multi-pin skews and etc.. But definitly cost effective and easy to establish high data bandwidth. Afterall, it is up to the system quality. Using well designed channel MB or using cost effective MB. Everything needs the price to pay.
Very interesting and very useful article about DRAM type selection !!! Well done !!!
Good overview!
Sr Product Manager
4 年A great primer on memory IP, thanks Ronen
AE Director EMEA at Cadence Design Systems
4 年Great overview and great point on the different ways a DDR PHY can be described from a PPA perspective... for such a standardized protocol like DDR, PHY PPA should follow a standard as well... ;-)