What are the various JTAG Instructions used in Boundary Scan ?

The prerequisite to understand JTAG Instructions are JTAG and its components ; which has been discussed in a post linked below:

https://ankitsfsj.wixsite.com/dftvlsi/post/what-ieee-standard-1149-1-1990-entitled-standard-test-access-port-and-boundary-scan-architecture

The IEEE 1149.1 standardizes the use of certain instruction so as to perform Boundary Scan related operations/tests. They can be divided into two categories:

1. Mandatory Instructions : these instructions must be implemented. The mandatory instructions include : a. Extest b. Bypass c. Sample/Preload
2. Optional Instructions?: these instructions can/cannot be implemented based on the designer's discretion. The optional instructions include : a. Intest b. Runbist c. Clamp d. Idcode e. Usercode f. Highz

Every instruction has an instruction code and first we need to load that instruction code using the TAP controller to perform that particular operation.

The steps of how to load an instruction has been discussed in a article linked below:

https://ankitsfsj.wixsite.com/dftvlsi/post/what-are-the-various-jtag-registers-used-in-boundary-scan-what-are-their-purpose

The JTAG specified instruction codes are:

• EXTEST = 000...... (all zeros)
• BYPASS = 111...... (all ones)
• other codes are specified by the designer

Now let us study the mandatory instructions and intest in detail:

EXTEST

• External test , selects the boundary scan register (BSR)
• Tests external off chip wire interconnections among chips
• Instruction code is 000...... (all zeros)

Steps for EXTEST instruction:

Step1: Scan in chip#1 : shiftDR = 1 , clockDR.....

Step2: Update chip#1 : updateDR

Step3: Capture chip#2 : shiftDR = 0 , clockDR....

Step4: Scan out chip #2 : shiftDR = 1 , clockDR.....

Keep mode signal always 1

BYPASS

• Bypass Scan Data from TDI to TDO of a chip
• Selects the bypass register (1 bit BR)
• Saves test time
• Instruction code is 111...... (all ones)

???????????????????????????????????????????????????SAMPLE/PRELOAD

• Sample : Take snapshot of system I/O pins
• Preload: Control system I/O pins (by output FF of the BSC)
• Instruction code is decided by designer

Steps for SAMPLE instruction:

Step1: Capture : shiftDR = 0 , clockDR

Step1: Capture : shiftDR = 1 , clockDR.......

Mode signal is kept to 0 so that this operation does not interfere with normal operation of the chip

Steps for PRELOAD instruction:

Step1: Scan in : shiftDR = 1 , clockDR......

Step1: Update : updateDR

Mode signal is kept to 0 so as to isolate system logic

???????????????????????????????????????????????????INTEST

• Selects boundary scan register
• Internal test of system logic

Steps for INTEST instruction:

Step1: Scan in : shiftDR = 1 , clockDR.....

Step2: Update input BSR : updateDR

Step3: Capture output BSR : shiftDR = 0 , clockDR

Step4: Scan out : shiftDR = 1 , clockDR.....

Keep mode signal always 1

Sources:

https://www.intel.com

Semicon Shots

https://technobyte.org/

Wikipedia

Prom CM Li, NTU Lectures