What is Transition Delay Fault (TDF) mean in DFT?

A transition fault on a line makes the signal change on that line slow. The two possible faults are slow-to-rise and slow-to-fall types. For detecting a slow-to-rise fault on a line, we take a test for a stuck-at-0 fault on that line. This test will set the line to 1 in the fault-free circuit and propagate the state of the line to a primary output. Let us call this vector V2 and precede it with any vector V1 that sets the line to 0. Now the vector-pair (V1, V2) is a test for the low-to-rise transition fault on the line. Note that V1 sets the line to 0 and V2 sets it to 1. V2 also creates an observation path to a primary output. If the line is slow to rise then that effect will be observed as a 0 at the output instead of the expected value of 1. The basic assumption in this test is that the faulty delay of the signal rise has to be large, since the observation path may be, and often is, a short path.?

TDF can be of two types:

1. S2R - Slow to Rise - In this case the line is slow to rise from logic 0 to logic 1
2. S2F - Slow to Fall - In this case the line is slow to fall from logic 1 to logic 0

Unlike the Stuck-at Fault(SAF) detecting a TDF fault requires a two pattern sequence as explained in the previous paragraph.

Case1: Steps to test a Slow-to-Rise transition delay fault

1.Set the node Low

2.Cause a low to high transition (like a s-a-0 test)

3.Check output between normal and delay transition

Case2: Steps to test a?Slow-to-Fall transition delay fault

1.Set the node High

2.Cause a high to low transition (like a s-a-1 test)

3.Check output between normal and delay transition

Clock Requirements to test TDF fault:

?One clock to Launch the transition

?One clock to Capture the effect of the transition

?At-speed cycle time between clocks

Source:

- CMOS VLSI Design: A Circuits and Systems Perspective by Weste & Harris

- Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits by Bushnell & Agrawal

- Semicon Shorts

etc