What is semiconductor testing?

The first step in making semiconductor products is to design chips according to the required functions. Then, the chips are fabricated into wafers. Since wafers are composed of chips arranged repeatedly, when we closely examine a completed wafer, we can see many small grid-like structures on it, with each small grid equivalent to a chip. The larger the chip size, the fewer chips can be produced per wafer, and vice versa.

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Semiconductor design does not belong to the manufacturing process. The manufacturing process of semiconductor products can be roughly divided into wafer fabrication, packaging, and testing. Among them, wafer fabrication belongs to the front-end process, while packaging and testing belong to the back-end process. The fabrication process of wafers is also subdivided into front-end and back-end, with CMOS process usually belonging to the front-end, and the subsequent metal wiring process belonging to the back-end.

Figure 1 shows the semiconductor manufacturing process and its industry division. Industries engaged solely in semiconductor design are called fabless chip design companies. Typical representatives of this model include Qualcomm and Apple. Manufacturers responsible for wafer fabrication are known as foundries. They produce wafers based on designs from fabless companies. The most typical representative of this is TSMC. Korean companies like DB HiTek and Magnachip also adopt this model. Wafers produced by fabless design and foundry manufacturing need to undergo packaging and testing, which are handled by outsourced semiconductor assembly and testing (OSAT) companies such as ASE, JCET, Stats Chippac, and Amkor. Additionally, there are integrated device manufacturers (IDM) like SK Hynix, which encompass multiple segments of the semiconductor industry chain including design, wafer fabrication, packaging, and testing.

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As shown in Figure 1, the first step in the packaging and testing process is wafer testing. After packaging, the packaged chips undergo further testing.

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One of the main purposes of semiconductor testing is to prevent defective products from leaving the factory. Providing defective products to customers damages their trust, leading to a decline in company sales and financial losses. Therefore, meticulous comprehensive testing of products before they leave the factory is necessary. Semiconductor testing needs to test various parameters of the product according to its characteristics to ensure product quality and reliability. However, this requires investment in time, equipment, and labor, resulting in increased manufacturing costs. Therefore, many test engineers are working to reduce testing time and parameters.

Type of test?

Testing processes can be classified into wafer testing and package testing based on different test objects, and into three types: temperature, speed, and operational mode testing based on different test parameters (see Table 1).

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Temperature testing is based on the temperature applied to the test sample: in high-temperature testing, the temperature applied to the product exceeds the upper limit of the temperature range indicated in the product specifications by 10%; in low-temperature testing, the applied temperature is 10% lower than the lower limit of the specifications; and constant temperature testing is generally performed at 25°C. In practical use, semiconductor products must operate in various environments, so it is necessary to test the operating conditions and temperature margins of the products at different temperatures. For example, for semiconductor memories, the typical temperature range for high-temperature testing is 85-90°C, and for low-temperature testing, it is -5 to -40°C.

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Speed testing is further divided into core testing and rate testing. Core testing mainly tests the core operation of the test sample, i.e., whether the planned target functions can be achieved smoothly. For example, in semiconductor memories, the focus of testing is on various parameters related to information storage units. Rate testing measures the operating speed of the sample to verify if the product can operate at the target speed. With the increasing demand for high-speed semiconductor products, rate testing is becoming increasingly important.

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Operational mode testing is subdivided into direct current testing (DC Test), alternating current testing (AC Test), and functional testing: DC Test verifies direct current parameters such as current and voltage; AC Test verifies the specifications of alternating current, including input and output conversion times and other operating characteristics; functional testing verifies whether the logical functions operate correctly. For example, in semiconductor memories, functional testing refers to testing whether memory cells and surrounding circuit logic functions operate correctly.

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The object of wafer testing is the wafer, which consists of many chips. The purpose of testing is to check the characteristics and quality of these chips. Therefore, wafer testing requires connecting the test equipment to the chips and applying current and signals to the chips.

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The completed packaged products form pins like solder balls, and these pins can be easily connected to the test equipment. However, in the wafer state, special methods, such as probe cards, are needed to connect the two.

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As shown in Figure 2, the probe card serves as the interface between the wafer under test and the test equipment. The card has many probes that can directly connect the communication interface of the test equipment to the solder pads on the wafer, and many connecting wires are arranged inside the card to connect the probes to the test equipment. The probe card is fixed on the test head, and the wafer probe station precisely contacts the probe card with the solder pads on the wafer to complete the test.

After loading the wafer with the front side facing up, the probe card on the right side of Figure 2 is reversed so that the needle tips face downward, achieving accurate alignment with the solder pads on the wafer. At this point, the temperature adjustment device applies the corresponding temperature according to the testing requirements. The testing system transmits current and signals through the probe card, reads the chip signals, and then reads the test results.

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The probe card needs to be made according to the layout of the solder pads of the tested chip and the arrangement of chips on the wafer, and the probes need to be arranged repeatedly according to the chip arrangement. In fact, in practical operations, it is impossible to test all the chips on the wafer with just one contact. Therefore, in actual mass production processes, it is necessary to make multiple contacts, usually 2-3 times.

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Generally speaking, wafer testing proceeds in the following order: Electrical Parameter Monitoring (EPM) → Wafer Burn-in → Testing → Repair → Testing. Below, we will explain in detail the specific steps of wafer testing.

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I. Electrical Parameter Monitoring (EPM)

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Testing can screen out defective products and provide feedback on defects in products under development or in mass production for improvement. Compared to testing, the main purpose of electrical parameter monitoring is the latter, which involves providing feedback on the manufacturing process of wafers by evaluating the electrical characteristics of individual unit elements of the product. Specifically, before formal wafer testing, electrical methods are used to measure the characteristics of transistors and contact resistance of the wafer, verifying whether the tested product meets the basic characteristics proposed by the design and component departments. From the perspective of testing, it is to use the electrical properties of components to extract DC parameters and monitor the characteristics of each unit element.

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II. Wafer Burn-in

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The curve in the figure above shows the failure rate of products over the product lifecycle [the curve resembles a bathtub, hence called the bathtub curve]: Early failure period, during which the failure rate is high due to defects in the manufacturing process; After the manufacturing defects disappear, the product enters the random failure period, during which the failure rate decreases; After aging and wear, the product enters the wear-out failure period, during which the failure rate increases significantly. If products are provided to customers immediately after completion, early failures will increase customer dissatisfaction, and there is a high possibility of product issues such as returns.

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The purpose of "burn-in" is to identify potential defects in products and detect early failure conditions of products in advance. Wafer burn-in is the process of applying external stimuli such as temperature and voltage to wafer products to identify products with potential early failures.

III. Wafer Testing

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After screening out early failure products during wafer burn-in testing, wafer testing is performed using probe cards. Wafer testing is the process of testing the electrical performance of chips on wafers. Its main purposes include: early screening of defective chips, pre-elimination of potential defective products during packaging/assembly processes and analysis of their causes, providing process feedback information, and providing feedback on components and design through wafer-level verification, etc.

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Part of the defective units screened out in wafer testing will be replaced by spare units (redundancy cells) in the repair process we will discuss below. To test whether these spare units can work normally and whether the chips can become qualified products, wafer testing must be performed again after the repair process.

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IV. Repair

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Repair, as a process in semiconductor memory testing, is the process of replacing defective units with spare units using repair algorithms. For example, if during wafer testing it is found that 1 bit out of 256 bits of DRAM memory is defective, the product becomes a 255-bit memory. However, if spare units replace defective units through the repair process, the 255-bit memory becomes a 256-bit memory again, which can be sold to consumers normally. It can be seen that the repair process can improve the yield of products. Therefore, when designing semiconductor memories, spare units are considered and defective units are replaced with spare units based on test results. Of course, producing spare units means consuming more space, which requires increasing the chip area. Therefore, it is not possible to produce sufficient spare units to replace all defective memories (such as producing spare 256 bits to replace all 256 bits). The quantity that can most effectively improve the yield should be selected considering the process capability. If the process capability is strong and the defect rate is low, fewer spare units need to be made, and vice versa.

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Repair can be divided into column (Column) units and row (Row) units: Spare columns replace columns where defective units are located; Spare rows replace rows where defective units are located.

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The repair of DRAM involves first disconnecting the column or row where the defective unit is located, and then connecting the spare column or row. Repair can be divided into laser repair and electronic fuse (e-Fuse) repair. Laser repair, as the name suggests, involves using lasers to cut off connections with defective units. This requires removing the protective layer around the solder pads on the wafer (Passivation layer) to expose the connecting wires. Since the surface of the chip after packaging is wrapped in various packaging materials, the laser repair method can only be used in wafer testing. Electronic fuse repair uses high voltage or current to disconnect defective units from the connection lines. Unlike laser repair, this method completes repair through internal circuits without the need to remove the protective film from the chip. Therefore, this method can be used not only in wafer testing but also in packaging testing.

Package testing

Chips judged as good products in wafer testing need to undergo package testing after packaging, as problems may occur during packaging. Moreover, wafer testing tests multiple chips simultaneously, and the limitations of testing equipment performance may prevent it from fully testing target parameters. In contrast, package testing is performed on a per-package basis, with relatively lower test equipment loads, allowing full testing of target parameters to select qualified products.

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The package testing method is shown in Figure 4: First, insert the "03" package pins (pins, shown as solder balls in the figure) into the package test socket with the pins facing downward, aligning the pins with the pins inside the socket, and then fix the package test socket to the package test board to perform the test.

I. Aging Test (Test During Burn In, TDBI)

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As mentioned earlier, "aging (Burn in)" is to detect early failures of products in advance by applying external stimuli such as temperature and voltage to wafer products. This process can be performed during wafer testing or in the packaging testing stage. The aging conducted after packaging is called aging test (TDBI). Most semiconductor products undergo aging tests during wafer and packaging testing to comprehensively grasp the characteristics of products, find conditions to reduce aging time and the number of processes. It can be seen that aging is the most effective process for mass production.

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II. Testing

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This is the process of verifying whether the operation mode defined in the data sheet can work normally in the user environment. Through temperature testing, defects in AC/DC parameters are checked, as well as whether the operation of unit & peripheral circuits (Cell & Peri) meets customer requirements. At this time, testing needs to be performed under conditions that are worse than those specified in the data sheet, and even under the worst conditions.

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III. Visual Inspection

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After completing all the tests, the test results and speed characteristics (especially when distinguishing speeds) are recorded on the surface of the product package through laser marking. After packaging testing and laser marking, the qualified products are placed into packaging trays (Tray) and can be shipped.

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Of course, before leaving the factory, a final test is required - visual inspection, to remove defects in appearance. Visual inspection mainly checks for cracks, marking errors, and incorrect tray loading, while regarding solder balls, it mainly checks for flattening or detachment of balls."