What Is a Practical PCB Design and How Does It Help You
Chun-Ting "Tim" Wang Lee, PhD
SI Application Scientist at Keysight Technologies
Introduction
As engineers design printed circuit boards (PCBs) to operate at higher data rates, the signal integrity of the system becomes increasingly sensitive to the variation in the fabrication process. A practical design is a software-defined design that includes realistic fabrication variation.
Typically, the PCB material properties in an Electronic Design Automation (EDA) software have default values. These ideal values for the material properties and PCB cross-sectional geometry are often called the as-designed values. The as-fabricated properties are the measurable numbers and dimensions from a physical board after fabrication.
Although these ideal, as-designed values provide adequate performance prediction, it is increasingly important to include as-fabricated values for material properties and cross-sectional dimensions in the simulation to achieve first-pass product success and reduce the number of board spins.
The focus of this article is the impact of the etch-back and the dielectric loss tangent. I'll talk about their impact on signal integrity, how to better characterize them, and how to include them in your practical design to better predict performance.
Impact of the etch-back
The as-designed, ideal trace cross-section is a perfect rectangle. In reality, however, a fabricated trace cross-section often resembles a trapezoid. See the figure below.
The characteristic impedance of a cross-section is proportional to the resistance per unit length (PUL) and the inductance per unit length (PUL) of the structure. When the etch-back decreases the cross-section area, both the resistance PUL and inductance PUL increase.
As a result, this trace etchback increases the trace impedance, so that the as-fabricated impedance is higher than the as-designed. See the numerical example in a previous blog post. The narrower the starting trace width, the more impact trace etch-back has on the as-fabricated impedance.
By including the etch-back in the simulation phase of each design iteration, engineers can design boards that are less susceptible to fabrication variation.
Impact of the loss tangent
The loss tangent has many names in the industry. Some call it tan-dee, some call it Df, some call it dissipation factor, and others tan-delta. Regardless of the name, it informs a designer of how much electrical energy is dissipated and not transmitted in a dielectric material. With a larger Df number, more electrical energy is dissipated.
A typical FR-4 (fire-retardant 4) material has a Dk (dielectric constant) of 4.4 and Df around 0.02. A high-speed material from Isola I recently came across in DesignCon ‘24 has a Dk of 3.1 and Df at 0.0015.
The description of the Isola material states [1], “[this material] has been engineered for very high data rates of >100 Gb/s [...].” Let’s examine how the low Df impacts the highest operating data rate.
From Dr. Eric Bogatin’s Rule of Thumb, the maximum attenuation (insertion loss) at the Nyquist for an acceptable eye-opening is about -10 dB without equalization [2].
Let’s assume we have a 5-inch trace made from a perfect conductor, so only the dielectric contributes to the insertion loss (IL). We can extend the dielectric loss relationship in [3] to approximate how high of a data rate we can run on the low-loss material. The approximation is
where DataRate is in Gbps, IL is insertion loss in dB, Df is the dissipation factor, Dk is the dielectric constant, and len is the trace length in inches.
Assuming the acceptable attenuation is 10 dB, for FR-4, where the Dk = 4.4, Df = 0.02, and considering only dielectric loss, the highest date rate = 47.7 Gbps.
For the low-loss material where the Dk = 3.1 and Df = 0.0015 and considering only dielectric loss, the highest data rate = 757.3 Gbps.
Considering the dielectric loss alone, one sees that our estimation confirms Isola’s claim that the operational data rate is greater than 100 Gbps.
领英推荐
By finding the correct value loss tangent, engineers can better predict the performance of the channel, knowing when the design has met the requirements.
How to better characterize the etch-back and loss tangent
Etch-back
The most straightforward way of looking at the etch-back is through a cross-section analysis. PCB cross-section analysis is a destructive process that involves cutting a small section of the PCB to examine its internal structure and quality. With the help of my advisors, I have developed a non-destructive technique to get an effective etch-back [4].
Loss tangent
In the high-speed industry, the clad measurements of dielectric are the most common, where metal conductive layers sandwich the dielectric material. This method provides a more realistic representation of the dielectric properties of the actual PCB, considering the presence of the copper layers and their impact on the overall performance [5].
Intel’s Delta-L technique is a good example of a clad measurement [6]. It provides transmission lines of different lengths as test coupons to extract the insertion-loss-per-inch measurement.
Then, the measurement-based model is usually used to extract the loss tangent of the dielectric from the results. A loss tangent extraction process might look like this:
How to create a practical design
To create a practical design that accounts for realistic fabrication variation, engineers must integrate the characterization of the etch-back and the loss tangent into the design and analysis process. Here are key steps to achieve this:
To quickly include your as-fabricated loss tangent and etch-back in your board-level simulation, consider Electrical Performance Scan (EP-Scan). EP-Scan is a signal integrity analysis software that takes in PCB board layouts and gives you S-parameters, Eye diagrams, TDR, and simulation reports in minutes. It also detects return plane discontinuities.
Conclusion
Integrating as-fabricated material properties like the etch-back and loss tangent into PCB design and analysis is essential for ensuring signal integrity and fabrication success, particularly in high-speed applications. By characterizing these parameters and incorporating them into the design process, engineers can create practical PCB designs that meet performance requirements and are less susceptible to fabrication variation.
Reference
[1] Isola, “TERRAGREEN? 400G2 Laminate and Prepreg,” [Online]. Available: https://www.isola-group.com/pcb-laminates-prepreg/terragreensup-sup-400g2/
[2] E. Bogatin, "How much attenuation is too much? Rule of thumb #10," EDN, 2011. [Online]. Available: https://www.edn.com/how-much-attenuation-is-too-much-rule-of-thumb-10/
[3] E. Bogatin, Signal and Power Integrity - Simplified (Signal Integrity Library), 2nd ed. Prentice Hall, page 383, 2017.
[4] T. Wang-Lee, "Test Structures and Economical Non-Destructive Measurement Techniques for Multilayer Printed Circuit Board Impedance Characterization," ProQuest Dissertations and Theses, 2020. [Online]. Available: https://www.proquest.com/dissertations-theses/test-structures-economical-non-destructive/docview/2474825547/se-2.
[5] James Baker-Jarvis et al., "Dielectric and Conductor-Loss Characterization and Measurements on Electronic Packaging Materials," Tech. Rep., 2020. [Online]. Available: https://nvlpubs.nist.gov/nistpubs/Legacy/TN/nbstechnicalnote1520.pdf.
[6] Intel, "Electrical characterization design methodology," [Online]. Available: https://www.intel.com/content/dam/www/public/us/en/documents/guides/electrical-character-design-meth-guide-337658-rev001.pdf.
Sr. Electronics Design Engineer Medical Systems
8 个月Surface roughness (mean) == Surface roughness (Rz), yeah, thats a silver-lined fantasy. However, up to 1GHz, it might as well be.
Well done, Dr. Tim. This clear and concise article is helpful to both signal integrity engineers as well as PCB Layout Designers. The as-designed vs. as-fabricated analysis is becoming even more critical for optimal interconnect design in today's faster serial data rates.