What is Pad to Pad (PP) ?

Pad to Pad or PP is an important design parameter in printed circuit board (PCB) design that refers to the spacing between the centers of two adjacent pads or footprints on the board. It determines how far apart components and their termination points can be placed from each other. Choosing the right PP distance is crucial in meeting PCB design rules and fabrication requirements. This article will provide an in-depth understanding of PP, how it impacts PCB design and manufacturing, and some best practices to follow.

What is Pad to Pad Spacing?

Pad to pad spacing, abbreviated as PP, is the center-to-center distance between two adjacent pads on a PCB. Pads are the metalized areas on the board to which component leads or terminations are soldered to establish electrical connections.

The PP defines how close two pads can be placed next to each other on the PCB layout. It is an important spacing rule that impacts routing, component placement, manufacturability and reliability of the board.

Factors that determine the Pad to Pad clearance include:

• Component package size and pin pitch
• Routing constraints between adjacent pads
• Manufacturing capabilities
• Electrical spacing rules and isolation requirements
• Mechanical spacing for rework and inspection
• Thermal considerations and heat dissipation

Why Pad to Pad Spacing is Important?

Maintaining proper pad to pad spacing is critical in PCB design. Here are some key reasons why PP clearance matters:

Routing and Component Placement

Adequate pad spacing makes routing traces and placing other components easier between pads. Tight PP can cause routing congestion.

Manufacturing Capabilities

The PP clearance must account for manufacturing tolerances of PCB fabrication equipment. Inadequate spacing risks short circuits.

Electrical Spacing Rules

PP spacing determines electrical isolation between traces/pads. Insufficient clearance can cause crosstalk or electrical shortage.

Thermal Management

Larger PP spacing allows heat dissipation, whereas smaller spacing can cause thermal hotspots.

Serviceability and Rework

Components and pads spaced closed together make rework, soldering and de-soldering difficult during assembly or repairs.

Reliability

Shorter pad to pad clearance provides less tolerance against solder bridges, environmental factors and noise interference over product lifetime.

Typical Pad to Pad Clearance Values

While the minimum pad to pad spacing depends on electrical and physical requirements, some general PP clearance guidelines are:

Pad SizeMinimum Pad to Pad≤ 200 mils8 mils≥ 200 mils16 mils

• Minimum PP is often set to 8 or 10 mils for standard density boards
• For high density PCBs, PP may be reduced to 6 mils or even 4 mils
• Spacing of 20 mils or above is common for larger pad sizes
• Clearance can be increased by 2-4 mils for multilayer boards

Here are some typical pad to pad clearance values used in PCB design:

• 08005 and 0603 sized SMT components: 8 mils clearance
• SOIC package ICs: 10 mils minimum
• QFP packages: 15 mils
• Through-hole pads: 20 mils or more
• BGA packages: 12 mils or higher
• High voltage pads: 30 mils or greater

However, the actual PP spacing requirements depend on many factors discussed earlier. These guidelines provide a typical reference range.

Calculating Required Pad to Pad Clearance

The minimum pad to pad spacing needed for a design is calculated based on:

1. Component Requirements

• Pin/lead pitch
• Pad size and shape
• Component placement density
• Package height over board
• Thermal characteristics

2. Electrical Requirements

• Trace routing rules
• Current carrying capacity
• Voltage levels and isolation needs
• Impedance control needs
• Electrical noise susceptibility

3. Manufacturing Capabilities

• Minimum feature size
• Hole wall tolerance
• Registration accuracy
• Copper thickness variance
• Finish thickness variance

4. Industry Standards and IPC Guidelines

• IPC-2221 Generic Standard on Printed Board Design
• IPC-7351 Generic Requirements for Surface Mount Design and Land Pattern Standard

By accounting for all these factors, the minimum PP clearance can be calculated to ensure the design meets both electrical and manufacturing needs.

How to Manage Pad to Pad Spacing in PCB Design?

Here are some tips on how to effectively manage pad to pad spacing in your PCB design and layout process:

Set PP Spacing Rules Upfront

Define pad to pad clearance rules and constraints early before placement and routing begins. This prevents violations later.

Use PP Design Rules in CAD Tools

Leverage PCB design software capabilities to set rules for minimum PP that will be automatically checked.

Control Grids and Component Density

Use component grids intelligently to regulate placement density. Higher grid sizes ease PP spacing.

Set Larger PP for Thermally Critical Parts

Give extra PP clearance between pads of components that generate significant heat like power devices.

Define PP Per Net or Between Classes

When nets have different electrical needs, assign clearances per net or net class based on voltage and isolation needs.

Allow Greater PP for Multilayer Constraints

In multilayers, increase PP slightly to account for registration tolerance between layers.

Review PP During Placement Reviews

Check pad to pad spacing visually during design reviews to spot violations or hotspots early.

Run PP DRC Checks Before Release

Validate final design against PP spacing rules through DRC and make corrections.

Impacts of Inadequate Pad to Pad Spacing

Maintaining inadequate pad to pad clearance can jeopardize the design and product function in the following ways:

Routing and Congestion Issues

Violating minimum PP can cause routing congestion and generate autorouter failures.

Component Placement Constraints

Components may need to be placed farther apart to satisfy PP rules, impacting board space.

Short Circuits and Electrical Failures

Inadequate PP risks solder bridges or electrical shorts during manufacturing especially for fine pitch parts.

Signal Integrity Problems

Smaller PP than needed can increase parasitic capacitance and cause signal noise or crosstalk.

Thermal Management Issues

Components not adequately spaced can suffer from thermal hotspots and overheating damage.

Difficulty in Rework and Soldering

Very tight PP makes manual soldering or de-soldering challenging for rework and repairs.

Long Term Reliability Risks

With no tolerance buffer, tightly spaced pads are prone to shorting from vibration, dust, moisture over time.

Fabrication and Assembly Problems

PP violations may cause PCB fabrication rejects or assembly difficulties.

Added Time and Cost

Fixing PP violations late in design process adds time and cost. It can even warrant a board respin.

Pad to Pad Spacing in Common PCB Features

Proper pad to pad clearance is necessary across all pad types and circuit features on a PCB. Here are some important considerations:

Surface Mount Lands: Sufficient clearance between fine pitch component termination pads.

Through-hole Pads: Adequate spacing between drilled pad barrels and edges.

Vias: Minimum PP between via pads and other pads or traces.

Testpoints: Added spacing for probe access between crowded test points.

Headers: Extra side to side clearance between header pin rows.

Holes: Spacing from hole edges to adjacent pads and traces.

Fiducials: Adequate clearance between fiducial pads and other features.

High Power Pads: Greater isolation space between pads of power devices.

High Voltage Pads: Larger electrical PP spacing for safety isolation.

Decoupling Capacitors: PP to support shortest path placement near IC pads.

Pad to Pad Spacing Variations by Layer

Pad to pad spacing design rules can be varied in multilayer PCBs based on differences in fabrication tolerance between layers:

External Layers: Tightest PP spacing allowed due to best registration accuracy.

Mid Layers: Slightly larger PP required since registration is not as precise.

Buried Layers: Maximum PP clearance needed owing to potential layer misalignment.

4 Layer Boards: ~2 mil increase in PP from external to buried layers.

6-8 Layer Boards: ~3 mil increase in minimum PP from external to buried layers.

High Layer Count PCBs: Up to 5 mil increase in PP spacing for buried versus external layers.

Pad to Pad Clearance in Common PCB Guidelines

Various PCB guideline documents prescribe recommendations for minimum pad to pad spacing. Some key standards are highlighted below for reference:

IPC-2221:

• 8 mil minimum PP for pad size up to 50 mils
• Clearance increased for larger pads and higher voltages
• Mid to inner layer PP relaxed by 2 mils

IPC-7351:

• 8 mil minimum PP for pad size below 200 mils
• 12 mil minimum over 200 mils pad diameter
• Spacing relaxed for higher pad aspect ratios

IPC-6012:

• Minimum clearance per IPC-2221 Class 3
• PP requirements customized based on performance class
• Considerations for thermal relief, plane gaps, etc.

IPC-7093:

• 10 mil minimum PP for 0603 and smaller components
• 8 mil PP allowed, where trace routing permits
• 12 mil minimum PP for SOIC packages

Pad to Pad Spacing Design Examples

To illustrate appropriate pad to pad spacing in different scenarios, some example cases are provided below for reference:

0402 Chip Resistor/Capacitor:

• Pad Size: 23 x 37 mils
• PP Clearance: 8 mils minimum

SOIC-8 IC Package:

• Lead Pitch: 50 mils
• Pad Size: 40 x 60 mils
• PP Clearance: 10 mils

QFN Package with 0.5mm Pitch:

• Pad Size: 12 x 12 mils
• PP Clearance: 4 mils minimum

DIP IC with 0.1" lead pitch:

• Pad Diameter: 45 mils
• PP Clearance: 20 mils

BGA Package with 1mm pitch:

• Pad Diameter: 12 mils
• PP Clearance: 8 to 12 mils depending on voltage and layer

Frequently Asked Questions on PCB Pad to Pad Spacing

Q1. How is minimum pad to pad clearance determined?

Minimum PP clearance is calculated based on electrical spacing needs, component specifications, manufacturing capabilities, industry standards and other mechanical and thermal requirements.

Q2. Can pad to pad vary based on layer in multilayer PCB?

Yes, generally pad to pad spacing is tighter on external layers and larger on internal layers to account for registration tolerance.

Q3. Does smaller pad spacing always improve PCB density?

Not always. If PP is too small, routing complexity increases and component placement flexibility reduces, lowering optimization. Moderate PP with good design helps maximize density.

Q4. What are typical PP clearance values for 0402 and 0603 packages?

For 0402 size, PP of 6 mils is common. For 0603 size, 8 to 10 mil PP clearance is standard.

Q5. When does pad to pad spacing become a critical factor?

PP spacing becomes critical for high density boards, smaller components, high pin count packages, buried passive designs, and high voltage applications.

Conclusion

Defining appropriate pad to pad spacing is vital for optimizing PCB design in terms of performance, manufacturability and reliability. By understanding PP clearance principles, electrical and physical constraints, standard guidelines and good layout practices, designers can effectively manage this key parameter. Sufficient pad to pad spacing provides routing flexibility, adequate electrical isolation and allows for manufacturing tolerances. Balancing these factors will enable determining the most suitable PP for a given design.