What is Memory Test & Repair in VLSI?
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What is a Memory test?
Memory test in VLSI is the process of testing the functionality of the memory blocks in an IC during the manufacturing test. Memory testing is performed using dedicated DFT instruments that generate test patterns applied to the memory under test and then compare the stored data with the expected results.
MBIST architecture at the chip level
Memory faults
A memory test algorithm is a finite sequence of test elements used to test the memory cell. The test elements consist of the following:
The test time (complexity) of an algorithm is expressed in terms of N (N = memory size)
Higher complexity means longer test time.
Algorithms like the March algorithm are used for detecting memory faults.
Faults detected by the March algorithm
Stuck-At Faults
In this model, a memory cell is permanently forced to a logic 0 (stuck-at-0 fault) or logic 1 (stuck-at-1 fault) value irrespective of any value written to the cell.
How to detect Stuck-At Faults?
A logic 1 must be read from the cell under test to detect the stuck-at-0 fault while a logic 0 must be read to detect the stuck-at-1 fault.
Stuck-Open Faults
In this model, a memory cell can’t be accessed which could be due to an open word line.
How to detect stuck-Open Faults?
The faulty memory cell can have either x or 1, continue reading....