What is JTAG Test Access Port (TAP) ? What is TAP FSM Controller ?
The IEEE 1149.1 standard has a set of standard ports, all boundary scan compliant devices have to follow this standard. The set of ports are called Test Access Port (TAP). Below are the JTAG ports also called the TAP:
The TAP controller is a 16-state FSM that responds to the changes in the TMS and TCK ports of the Test Access Port. The use of the TAP ports can be understood upon studying TAP FSM.
The Data Register (DR) is depicted by the yellow blocks on the left, while the Instruction Register (IR) is represented by the green blocks on the right. In the upper left corner, we find ourselves in the test logic reset state, our ideal starting point. There are two methods to return to this reset state:
Method1: Apply a test logic reset by setting TRST port of TAP to 0.
Method2: Continuously apply a sequence of 1s.
Q.) Here comes a question : Why is the TRST pin of TAP an optional pin ? How many sequences of 1s are needed to reset the TAP ?
Ans:) The? Method 2 discussed above is the reason why the TRST port is an optional port , which shows that even without a TRST port we can use a sequence of 1s to reset the design. The maximum sequence of 1 required is ‘five’. If we trace the red line in the TAP design,? we will get the answer.?
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The TAP FSM is under the control of the TMS and TCK ports. By altering the sequence of TMS and TCK we can transition into any state. Additionally, holding TMS at zero allows us to remain in a specific state. Thus the whole 16 state FSM is controlled by TMS and TCK.?
Sources:
Semicon Shots
Wikipedia
Prom CM Li, NTU Lectures