"Wanted" SI EE's - Testing for RX Margin in the Lab or Fab #DesignCon

#DesignCon is a great place to network, get a peak at roadmaps in keynotes before the general public, you can also influence final product with input (if it only had this) Who better to ask if we got it right than the worlds collection of SI engineers with varied backgrounds? Granted, it also lets competitors look at things and spur on healthy discussions that, in the end, benefits the consumer.

Recall (years ago) doing booth duty, showing a 100 GHz solution when a CTO at the largest T&M company on the planet, stop and said something like - that cant be live, that's years ahead of us. Watching our Chief Scientist discuss the challenges, it reminded me of two solders meeting off the battlefield, the mutual respect and the shorthand conversation. Back then, they left me at the train station.

Multilane is known as an "early adopter" "quick reactor" as well as Data Center test solutions provider. Always known for bringing solutions to market while others are still trying to understand if there is a problem they can leverage. . Yes, we look for problems to solve in the engineering world around High speed IO and Signal Integrity. We even supply data center tool kits to get you up and running We even loan people out to help our clients get to market faster by focusing a large team on a specific problem. It stresses bandwidth but we learn a lot. Not a streamlined design but one that puts the customer out front.

FY23 its no different - Instead of showing our solutions in the old perfectly controlled demo. We will be testing live, on other vendor prototypes or recently introduced products (some delivered days before or "Day of" . Yes its Chaotic, last minute and wont always be pretty - But lets not forget I've seen your labs and when product launch comes around you truly live in the "Eye of the Storm"

Stop by booth #749 (here's a free pass) join engineers for a peak at "Next Gen" products, meet the designers, get insight on the best ways to test PHY layer High Speed protocols, with a focus on #signalintegrity in the Lab, Fab or Production floor - Meaning our solutions scale from world leading measurement specifications for the R&D Lab to production (cost effective) and now wafer level test - I heard a clever design engineer remark in her presentation at our last summit - From a cable, chip or test rack, We always have your back.

So if you want to do Receiver margin testing on your design Lab or Fab environment, now's the time for your voice to be heard - As CTO/CEO and design EE's will be in the booth (PM me if you want a private chat) otherwise take your chance, roll the dice and drop in.

Ill try to update with info during the expo as some of you cant make it this year. If your an SI engineer and want to drop off a resume try looking here first or ask for me at the booth

Dan Payne (chief Bottle washer at large)

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