Wafer Level System in Package (SiP)
Dieter G. Weiss
in4ma (information 4 manufacturers) Qualified Market Research about the European EMS/ODM industry and support for the OEM industry to find the right manufacturing service partner
Everybody is talking about the chips act, but the western world is not only dependent on chips but on first level packaging as well. There is not only insufficient capacity but as well insufficient knowledge about the technological possibilities.
Today I informed myself at #ASMPT HQ in Singapore about their Wafer Level System in Package (SiP) capabilities. They call it the #SIPLACE CA2, an assembly system, which allows to assemble dies directly from the wafer (w/o tape) onto a bigger base wafer either in flip chip or die-attach technology as well as placing SMD components and small ceramic hybrids onto the wafer basis as well.
The wafer can be up to 12 inches in diameter and placement accuracy can be up to 10 micron.
The technology is there and in bigger OEMs, System in Package applications are already used. Now it is the time for designers in the EMS industry to show the market, that there are such technologies available in the service industry as well.
SiP not only improves functionality but as well pushes electronic systems to further miniaturization and thus reducing scrap from end of life electronic products.
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2 年Very happy how impressed you had been by our SIPLACE CA! Thanks again for visiting ASMPT Ltd in Singapore ???? ASMPT SMT Solutions