VLSID 2025

#VLSID2025 #Ignitarium #AI #Silicon #IBM #TATAELECTRONICS #ESD #DFT #VLSID #VLSIDCon #EmbeddedSystems #Semiconductors #AIinSilicon #ICPackaging

I had the incredible opportunity to attend the VLSID Conference 2025, a premier event for VLSI professionals and enthusiasts. The event offered invaluable insights into the latest trends, and the four tutorials I attended were particularly enlightening.

Thanks to Ignitarium Sujith Mathew Iype Nishi Anna for granting me this opportunity.

It was such a privilege to attend the VLSID 2025 conference - The 38th International Conference on VLSI Design. The theme is Silicon meets AI - Sustainable Innovations in Accelerated Computing, Secure Connectivity & Intelligent Mobility.

I had the opportunity to attends 4 tutorials where experts in each field showcased their technical dominance in each domain

Tutorial 1: Introduction to AI Inferencing Hardware by Dr Rahul M Rao and Preetham M Lobo from IBM

This session demystified how hardware architecture supports the demands of AI inference.

Agenda:

• AI Introduction
• AI inferencing and HW architecture of accelerators
• HW/SW Codesign
• Power management
• Survey of AI Accelerators
• Summary and Conclusion

Key Takeaways:

• AI - Technique that enables machines to mimic cognitive functions associated with Humam minds
• ML based systems are trained on historical data to uncover patterns
• Data learning is a subset of ML using multiple layers of neural networks
• Generative AI systems (Foundational model) - AI model using a specific kind of neural network called a transformer like GPT
• Matrix multiplication and activation functions are critical operations in AI models, and their execution accelerates two main components of the machine learning workflow: Computational efficiency and model expressiveness
• AI training: The process of teaching the AI model using large datasheets to recognize patterns and make predictions. It involves arriving at the model parameters
• AI inference: Applying a train model to new data to generate predictions or classifications without human intervention. It is a subset of training.
• MAC - The hardware building block: The fundamental HW block to realize a neuron is the Multiply-and-ACcumulate unit. It has 3 inputs - Filter weight, activation input and partial sum, 1 output result. To achieve higher performance on compute, the MAC unit can be parallelized.

An example neural network was showcased to recognize handwritten digits from a MNIST database.

• Process: With 10 output neurons, hidden layer has 784x16 weights + 16 biases, output layer has 16x10 weights + 10 biases. Totally 12,704 weights + 26 biases (12730 paramaters)

• HW/SW codesign: The goal is to achieve maximum accuracy with less energy and cost. There are 2 approaches to achieve this - reduce precision of numbers, reduce number of operations and model sizes
• Power management: Power consumed follows compute utilization which can vary significantly. A power management architecture for AI workloads to optimize performance across different peak current needed.

Conclusion:

• Generative AI is driving explosive growth in AI Hardware acceleration
• Optimization will be required across the HW/SW stack based on model
• Broad areas of innovation in HW will be in compute efficiency and communication bandwidth

Tutorial 2: Digital Circuit Testing and Testability by Indranil Sengupta, IIT KGP

A comprehensive overview of testing techniques critical to ensuring the reliability of digital circuits.

Key Takeaways:

• Design for Testability (DFT) is an essential process in VLSI design aimed at enhancing the ease and efficiency of testing integrated circuits (ICs).
• Importance of DFT in VLSI PD - Yield Improvement, Cost Efficiency, High Reliability
• Fault models in Design for Testability (DFT) provide a systematic way to identify, analyze, and test defects in VLSI circuits. These models represent the possible defects that may occur during the manufacturing of integrated circuits, helping generate efficient test patterns to detect them.
• Stuck-at Fault Model - Assumes a signal line in a digital circuit is permanently "stuck" at logic 0 (stuck-at-0) or logic 1 (stuck-at-1).
• Transition Fault Model - Focuses on timing-related defects where a signal transition (0→1 or 1→0) fails to occur within the required time. Represents slow-to-rise and slow-to-fall defects.
• Path Delay Fault Model - Targets the entire delay of signal propagation along a specific path in the circuit. Detects performance-related issues caused by interconnect delays or marginal devices.
• Bridging Fault Model - Models defects caused by short circuits between two signal lines (bridging faults). The faulty line might act as dominant (AND or OR behavior) or undefined.
• Open Fault Model - Simulates situations where a signal line is broken (open circuit), leading to floating states.
• Key DFT Techniques in PD - Scan Chain Insertion, Built-In Self-Test (BIST), Boundary Scan (JTAG), Automatic Test Pattern Generation (ATPG)
• Emerging Trends - Test Compression, DFM-Aware DFT, AI-Driven Test Optimization

Tutorial 3: On-Chip ESD Design: Complexity in Simplicity by Nathaniel (Nate) Peachey, ESD Association

A deep dive into on-chip ESD protection, illustrating how simplicity masks underlying complexity.

Agenda:

• Introduction - Electrostatics and ESD risks in assembly
• On-chip ESD test models and Standards
• Transmissions of ESD Design architectures
• Protecting against the CDM event
• Summary

Key Takeaways:

• ESDA is a network of experts building a reliable network and equitable ecosystem in the theory and practice of EOS/ESD mitigation.
• Aims to collaborate and network building excellence in the theory and practice of ESD mitigation.
• Design of ESD protection circuits began in the late 1970s and early 1980s. This resulted from observing a rise of failures in assembly that could be attributed to electrostatic discharge.
• Advances such as Siticidation and LDD implants had been introduced to improve CMOS device performance.
• ESD protection at the chip/die level is ONLY intends to provide sufficient protection to survive the assembly process
• The test models used are Human Body Model (HM) and Charged Device Model (CDM)
• HBM - Simulates fingertip discharge of a charged person into metallic leads of a device, for discharges to a grounded device pin

• CDM - Field-Induced charged device model ESD Simulator

• TLP (Transmission Line Pulse) testing is a crucial methodology used in the characterization and design of Electrostatic Discharge (ESD) protection in semiconductor devices.
• Charge transmission line with HV supply
• Flip the switches A and B
• Measure the response near the end of the pulse
• Leakage measurement after each pulse used to determine failure
• ESD Design SOA curves, Pad-based protection, ESD design window and ESD design strategies were also discussed.

Summary:

• Fundamentals of ESD protection circuits and architectures were discussed
• Basics of device tests (HBM and CDM) were discussed
• Circuit elements as well as the various approaches for ESD protection were reviewed
• Impacts of 3D and hybrid bonds on ESD and ESD protection on levels were reviewed.

Tutorial 4: Introduction to IC Packaging by Raghavendra Anjanappa,Tata Electronics

This session covered the critical role of packaging in the functionality and reliability of integrated circuits.

Key takeaways:

• Semiconductor package types - BGA, QFN-8, QFP-44, DIP, QFN-16, QFP-100, DO-214AC, QFN-48 etc.
• Roles of a semiconductor package:

1. Electrical interface
2. Physical protection of die
3. Heat dissipation
4. Expand functionality

• Semiconductor packages - Stacking types

1. Package stacks
2. Chip stacks with wire bonding
3. Chip stacks with TSV

• Semiconductor packaging - Challenges

1. Thermal dissipation
2. Small form factor
3. Low cost
4. High reliability
5. Stacking
6. High speed signa; Transmission

• Package design workflow - TSAT

1. Design inputs overview
2. Die & BGA package creation
3. Stackup and constraint setup
4. Design feasibility netlist creation
5. Placement design
6. Pre-layout SI/PI Analysis
7. Route the design
8. Post SI/PI Analysis
9. Implement SI/PI feedback
10. QC approval
11. Manufacturing

• Semiconductor packaging current trends:

1. 2D - Chips are mounted horizontally on sbstrate
2. 2D+ - Chips are stacked on substrate and connected by bond wires
3. 2.5D - Integration through silicon interposer
4. 3D - Chips are connected directly through TSV

• Semiconductor packaging future trends:

1. 3.5D - Chips are connected directly through TSV, then interposer
2. 4D - Integration through substrate folding or bending

• The entire IC packaging process of wire band and flip chip, ESD Control for cleanroom, ESD damage prevention, Cleanroom procedure for FEOL and BELO were also explained

These tutorials have undoubtedly broadened my perspective in the VLSI domain. Kudos to the VLSID team for organizing such a fantastic event! Have you attended similar conferences or tutorials recently? I’d love to hear your thoughts!