VHDL or Verilog, which one is important? learning VHDL could be useful?

Both VHDL and Verilog HDL (Hardware Description Languages) are very important to learn, and they both are in wide use across all the designs/IPs, "replacing them is a nightmare", though System Verilog can be used for design due to its inherent nature, but its mainly considered for Verification HVL (Hardware Verification Language) due to its extensive features!

On the other hand, VHDL is considered to be an important language in FPGA designs, due its strongly typed and detailed description nature! If you are working in any defense based applications you might have encountered VHDL is preferred for design implementation, considered to be a security reason!

Which one should I learn VHDL or Verilog to begin career as VLSI designer?

Well, VHDL considered to be harder to learn than Verilog (as many of as aware), that is due to its inheritance from ADA based language unlike Verilog which inherited from C language (familiar to all of us), so in simpler words, Verilog is easy to learn and compact!

VHDL is harder to learn and descriptive!

Note to add: Learning harder language make your life much easier and understandable!

Comment below for more details!

Thanks

Prasanth S