VHDL & C++

This prelude is neither about VHDL nor about C++ indeed it's about "to add some C++ codes to VHDL codes" or to put it in better way to add Microcontroller to your FPGA. Here I'll do the most simple project I could come up with for a System on Chip Hello World example (HellowSoC).

The system uses four switches to drive four LEDs. Two LEDs and two Switches are connected to RTL unit and other two LEDs and Switches are connected to Microcontroller unit. The firs LED is switched purely through RTL module and the last LED is switched purely through Microcontroller. Second switch is connected to RTL unit and its value goes to Microcontroller which sends it to third LED. Third switch is connected to Microcontroller unit and its value goes to RTL unit which sends it to second LED.

The aim of this example is to use both processing system (PS) and programmable logic (PL) simultaneously and to interconnect them.

In this tutorial I use Vivado Design Suite and Vitis Software Platform to program Artix-7 FPGA and to load MicroBlaze soft microprocessor inside it.

Phase 1: Hardware Design - Vivado Design Suite

• Launch Vivado > Create Project > Enter 'Project name:' ; Browse 'Project location' to the directory you want to store you project ; Check the box for 'Create project subdirectory' ; Select 'RTL Project' and check the box for 'Do not specify sources at this time' ; Select you FPGA from 'Parts' tab (don't use 'Boards' tab at this time) ; 'Finish'

I use Arty A7 board which I downloaded its file from digilent and adding this board made the work easier but for the sake of learning don’t use this option and just select your FPGA. Mine is Family: Artix-7 and Speed: -1L and Package: csg324 => Xc7a35ticsg324-1l

• In the 'Flow Navigator' just under 'PROJECT MANAGER' click 'Settings' then choose as 'Target Language' and click 'OK'
• Click 'Add Sources' in the 'Flow Navigator' ; Select 'Add or create design sources' ; Click 'Create File' ; Choose 'VHDL' for 'File type' and enter "swled" ; 'OK' and 'Finish'
• In 'Sources' subwindow double-click 'swled.vhd' file and enter the following code:

libray ieee;
use ieee.std_logic_1164.all;

entity swled is
    Port ( sw : in std_logic_vector (1 downto 0);
           din : in std_logic;
           dout: out std_logic;
           led : out std_logic_vector (1 downto 0));
end swled;

architecture arch of swled is
begin
led(0) <= sw(0);
led(1) <= din;
dout <= sw(1);
end arch;

Now we have to draw diagram for MicroBlaze soft processor and the peripherals we need.

•  Click ‘Create Block Design’ in the ‘Flow Navigator’ and under ‘IP INTGRATOR’
• Enter 'Design name:' and click OK then 'Diagram' window sill pop up.

• Add 'MicroBlaze' IP by clicking '+' in 'Diagram' window
• Click 'Run Block Automation' on green stripe top the 'Diagram' window

Leave every thing at its default value and click OK

• Now 'Run Connection Automation' again on the green stripe
• Just check the box for 'All Automation' and click OK
• Add 'AXI GPIO' IP
• Double-click on the 'AXI GPIO' block and check the box for 'All Inputs' and change the number of 'GPIO Width' to 3 then check 'Enable Dual Channel' and this time check 'All Outputs' and enter 3 for 'GPIO Width'.

• Now click ‘Run Connection Automation of the green stripe and then check the box for ‘All Automation’ and click OK
• We completed block diagram and we have to run ‘Design Validation’ by pressing F6.
• Having seen the ‘Validation successful. There are no errors or critical warnings in this design.’ save the block design.

• In the ‘Sources’ subwindow, right-click on ‘ublaze(ublaze.bd)’ and select ‘Create HDL Wrapper …’ (I named my Block Design "ublaze")
• Select ‘Let Vivado manage wrapper and auto-update’ and then click OK
• After generating HDL wrapper, a VHDL file named ‘ublaze_wrapper.vhd’ will add under ‘Design Sources’. Double-click on it to see the VHDL code

Creating top VHDL file:

Now we have to create a top file to instantiate both RLT unit and Microcontroller unit. Click 'Add Sources' in the 'Flow Navigator' ; Select 'Add or create design sources' ; Click 'Create File' ; Choose 'VHDL' for 'File type' and enter "top" ; 'OK' and 'Finish'. Enter following code in top.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top is
port(
     diff_clock_rtl_0_clk_n : in std_logic;
     diff_clock_rtl_0_clk_p : in std_logic;
     rst : in std_logic;
     sw : in std_logic_vector(3 downto 0);
     led : out std_logic_vector(3 downto 0));
end top;

architecture struc of top is
signal d1,d2 : std_logic;
signal gpi, gpo : std_logic_vector(2 downto 0);
begin
rtl_unit: entity work.swled(arch)
port map(sw=>sw(1 downto 0), din=>d1, led=>led(1 downto 0), dout=>d2);

gpi <= sw(3 downto 2) & d2;
led(3) <= gpo(2);
led(2) <= gpo(0);
d1 <= gpo(1);

uC_unit: entity work.ublaze_wrapper(STRUCTURE)
 port map(
    diff_clock_rtl_0_clk_n => diff_clock_rtl_0_clk_n,
    diff_clock_rtl_0_clk_p => diff_clock_rtl_0_clk_p,
    gpio_rtl_0_tri_i => gpi,
    gpio_rtl_1_tri_o => gpo,
    reset_rtl_0 => rst
  );
end struc;

• In The ‘Flow Navigator’ and under 'RTL ANALYSIS' click 'Open Elaborated Design'
• You have to see the ‘I/O Ports’ menu at the bottom of the window, if not from the ‘Layout’ menu at the top select ‘I/O Planning’. It’s similar to ordinary FPGA project.

As I mention earlier, my board is Arty from Digilent. You have to place the signf s onto the appropriate I/O pin locations.

• Save the design constraint to create a ‘XDC’ file.
• Now from the ‘Flow Navigator’ do ‘Generate Bitstream’
• The last thing to do in Vivado is to generate hardware platform file. Select ‘Export Hardware…’ from ‘Export’ under ‘File’ menu. Select ‘Fixed’ then ‘Include bitstream’ to create 'top.xsa' file.
• Now 'Launch Vitis IDE' from 'Tools' menu.

Phase 2: Software Design - VITIS IDE

• Create a folder named "Vitis" inside your Vivado 'Project Location'
• In Vitis IDE from 'File' menu select 'Switch Workspace' and browse to "Vitis" folder you've just created.
• In the 'Welcome' windows click on 'Create Platform Project' and write a name for 'Project name:' (I named it "HellowVitis")
• Select 'Create from hardware specification (XSA)' click 'Next' and brows to 'XSA file' you've created in the last step of Phase 1 (We named it "top.xsa") and 'Finish'
• In Vitis select File => New => 'Application Project...' and then from 'Select a platform from repository' choose the platform you've just created in two step earlier "HellowVitis[custom]" and click 'Next'
• Enter a name for 'Application project name:' "hello" and click next and in 'SW development templates' select 'Empty Application' and 'Finish'
• In 'Explorer' subwindow right-click on 'src' folder to add a 'New' 'File' then write "main.c" in the box for 'File name:'

• Write the following code in "main.c"

#include <xgpio.h>

int main()
{
    XGpio input, output;
    int swd;
    XGpio_Initialize(&input,0);
    XGpio_SetDataDirection(&input, 1, 0xF);

    XGpio_Initialize(&output, 0);
    XGpio_SetDataDirection(&output, 2, 0x0);

    while(1){
    swd = XGpio_DiscreteRead(&input,1);
    XGpio_DiscreteWrite(&output,2,swd);
    }

    return 0;
}

• Save and Build: 'Ctrl + S' and 'Ctrl + B'
• Having attached your board to the computer, right-click on the highest hierarchy in 'Explorer' subwindow go to 'Rus as' and '1 Launch Hardware'

It's done and you must be able to switch the four LEDs.

A point about programming FPGA:

Vivado generates .bit file which contain all information about Hardware (VHDL) so if you write only this .bit file into the FPGA the hardware works well. In this example the purely hardware part drive the first LED via first switch other there LEDs and switches need software program to work. Vitis generates .elf file that contains your C++ code and .elf is akin to hex file for ordinary Microcontroller. You need to merge the .bit file generated by Vivado and the .elf file. To do so in Vitis from 'Xilinx' menu select 'Program FPGA': the .bit file has automatically added but you have to add .elf by clicking 'bootloop' under 'Software Configuration'. Now click 'Generate' and it creates download.bit file (.../Vitis/Hello/_ide/bitstream/download.bit)

You can use download.bit to 'Write Memory Configuration File' in Vivado an then program flash memory to store your whole system.

I hope this prelude should help those who use both FPGA and Microcontroller in their products separately and want to migrate to SoC.

Digilent Boards and Documentation were a great boon to me.

There is a surfeit of useful articles by Adam Taylor and Whitney Knitter: