VHDL-2019 Part 3: RTL Enhancements
In this third webinar of the VHDL-2019: Just the New Stuff series we will focus on enhancements to VHDL's RTL coding capabilities.
VHDL was more verbose than other languages - Not any more - VHDL-2008 banished verbosity and now VHDL is at least as concise as Verilog/SystemVerlog and much more self consistent. VHDL-2019 continues working to make VHDL more concise and expressive.
This presentation focuses on the following RTL enhancements:
- Conditional expressions in object declarations
- Conditional return
- Allow functions to know the output vector size
- All interface lists are ordered
- Inferring signal and variable constraints from initial values
- Optional trailing semicolon at the end of interface list
- Component declaration syntax regularization
- Range Expressions
Don't forget, I already covered VHDL Interfaces and conditional compilation in the Part 1, “VHDL-2019 Interfaces, Conditional Analysis, File IO, and The New Environment.” Both of these are significant improvements to RTL coding.
About VHDL-2019
VHDL-2019 was requested by users, ranked by users, scrutinized by users, written by users, and balloted by the VHDL community. As such, it should be clear to the vendor (simulation and synthesis) community that the users want these features.
Through its revisions, 1987, 1993, 2000, 2002, 2008, and now 2019, VHDL has evolved to be a capable design and verification language.
Aldec started their implementation of VHDL-2019 prior to the standard being completed and is well into their implementation. If your vendor cannot tell you definitively if and when they will support the new features you want to use on your VHDL projects, then maybe it is time to find a vendor who will.
What about Verilog and SystemVerilog? Despite overwhelming marketing for SystemVerilog, it is clear from the Wilson Verification Survey, that VHDL is the preferred FPGA design and verification language. For many applications, FPGA is the future. Just like in the software world, FLASH is usually preferred over ROM.
The VHDL standards committee work is never done. It takes a collaboration of people with different skills to successfully update the standard. Some of these members are language experts, some design experts, and some verification experts. Join us in writing the next revision. See: https://www.eda-twiki.org/cgi-bin/view.cgi/P1076/WebHome.
Presenter BIO
The presenter, Jim Lewis, is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and space craft.
Whether teaching, developing OSVVM, doing VHDL design or verification consulting, or working on the IEEE VHDL standard, Mr Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.
Enroll
Europe Session, May 27 3-4 pm CEST, 6-7 am PST, 9-10 am EST
US Session, May 27 11 am -12 noon PST, 2-3 pm EST, 8-9 pm CEST
Be sure to enroll with a work (or school) email.