Verilog HDL code for Half Adder

A half adder is a type of adder, an electronic circuit that performs the addition of numbers. The half adder is able to add two single binary digits and provide the output plus a carry value. It has two inputs, called A and B, and two outputs S (sum) and C (carry). The common representation uses an XOR logic gate and an AND logic gate.?

Truth Table & Circuit Diagram of a Half Adder

Verilog Implementation:

half_adder.v

// Half Adder Circuit Test Bench
// Md. Nahidul Islam
// 27 - Jun - 2021
  module half_adder (A , B , S , C );
         input A , B;?
         output S , C;
         xor ( S , A , B );
         and ( C , A , B );
                  

  endmodule?        

tb_half_adder.v

module tb_half_adder();
reg a , b ;
wire s , c;


half_adder ckt(a,b,s,c);


initial?
begin
	a = 1'b0;
	b = 1'b0;
	#100
	a = 1'b1;?
	b = 1'b0;
	#100
	a = 1'b0;?
	b = 1'b1;
	#100
	a = 1'b1;?
	b = 1'b1;


end?        

endmodule?        

Results of Simulation:

Fig- ModelSim Simulation Output