Verilog Course for FPGA and ASIC Design
· What HDL is: HDL (HARDWARE DESCRIPTION LANGUAGE) is a programming language that can be used for both modelling and then simulating a piece of hardware or digital system. Therefore, for designing a digital circuit and describing its all levels of abstraction, HDL is a golden tool.
· Who are main users of HDL? Application-Specific Integrated Circuit (ASIC) and Field Programmable Gated Array (FPGA) designers use HDLs for designing/modelling hardware requirements in different stages of their design flows.
· What are major in use HDLs? Verilog and VHDL are main players, and defined and supported by IEEE standards. Verilog which is the focus of this course was defined by IEEE standard 1366, it was then approved in 1995 as Verilog-1995 and revised in 2001 as Verilog-2001. The Verilog-2001 is the version being used by academia and industry.
· Now, its time to draw your attention to some points that you may like to know:
1. The course is based on Verilog-2001.
2. The prerequisites for the course include basic knowledge of basic logic gates, as well as Boolean algebra and some early knowledge of combinatorial and sequential major building blocks like decoders, encoders, multiplexers, de-multiplexers, latches and Flip-Flops, counters, registers and shift registers, and the basic of Finite State Machines.
3. The course is instructed in an industry oriented fashion rather than university-based approach; meaning that it can answer “how a basic digital system can be modelled/designed so that it can meet industry standards” rather than exploring complex aspects of Verilog itself in a syntax and features review manner.
· Is Verilog similar to C language? Syntax-wise: sort of
· What is the main difference between C and Verilog then? Verilog is established upon hardware modelling which is supposed to end up with a digital system that can function “concurrently”. C language, but is based upon sequential executions of a program which is not more than lines of high level man written computer codes.
· A typical ASIC/FPGA design flow should include but not limited to:
1. Design Entry: writing a text based description of a required digital system. Design entry can be based on a top-down or bottom-up hierarchical fashion; which will be discussed and instructed as a part of existing course. Design entry can be categorized in different descriptive fashions of modelling a digital system:
? Structural description: using gates, transistors, or even some complex modules as building blocks and connect (wire) them just like the way they would be connected on a schematic design.
? Behavioral description: describing what a module is expected to do in a high level functional/behavioral/bussing structure fashion.
Now it might be a right time to answer one frequent question, and that is nothing except “what RTL is?” RTL stands for “Register Transfer Level”, and it refers to digital system register descriptions and the way data gets transferred between those elements. RTL is a concept attached to high-level circuit description (behavioral modelling) all the time, and that is the reason somehow behavioral modelling and RTL coding can be exchangeable in semiconductor industry context.
2. Compile Phase: at this phase the written code in design entry step gets compiled in order to make sure the RTL code complies Verilog language syntax rules.
3. Functional Simulation: this key step is needed to verify that design would operate as intended. Functional simulation is vital, and never ever should be skipped or underestimated, as it can trap functional bugs and discrepancies between RTL code and design specification to a great extent. Functional simulation needs a Verilog based testbench that can orchestrate stimulus (test inputs to design) generation, as well as collecting all outputs to decide whether design is functional as intended or daffy. Testbench structuring and design verification can be a super complex, and time hunger task; however, a basic Verilog-based testbench will be presented. In terms of verifying complex semiconductor IPs, a System Verilog - UVM based testbench is needed, which is not a part of existing course.
· The Scope of Existing Course: during the course, the Verilog-2001 features and potentials, from design entry to functional simulation, in both conceptual and experimental contexts will be presented. Almost all examples will be ported to “Xilinx Vivado Design Suite 2018.2”, then will get compiled, and eventually Vivado simulation engine will get invoked in order to simulate and validate RTL code functionality. Having said that, a brief tutorial for creating a project in Xilinx Vivado Design Suite and taking advantage of all useful and interesting features from design entry to functional simulation will be experimented.
· As a sum up, existing course is the first part of a series of 10 courses, which instruct Verilog-2001 for modelling and simulation (if applicable) of essential logic primitives based on MOSFET transistors, where it can be applicable to ASIC/VLIS world for designing standard logic cells and can be considered as the lowest possible level of abstraction, as well as structural description of digital systems using primitive gates as the second most lowest level of abstraction for describing a digital system.
#Verilog, #FPGA, #ASIC, #VLSI