Verification interviews: the mood, the mad and the mugly!

Some random thoughts on interviews and interviewers.

I’m still on both sides of the coin, after over two decades of ASIC design. Hiring and being hired. And both are not always pleasant experiences. Hiring is hard, getting a role is hard as well. We are all individuals, and individuals have an ego. Sometimes it is just the use of a particular word. Or an opinion that triggers the ego to roar its ugly head. Especially on the candidate side, you are mostly on the receiving end. There is no such thing as accountability for interviewers. In theory there is, but practically, it is always a bad idea to call out (perceived) mischief. Today I want to talk to you about both sides of the coin. Specifically, in verification.

I personally don't like to write more on Linkedin since this site isn't kind to #semiconductor professionals. Our niche is too small to draw attention. That is why I started my blog. Therefor, I would kindly ask you to read the rest of the article on my blog: ASIC verification. Thank you very much in advance. Namaste!