UVVM at ESA's FPGA conference in The Netherlands

The European Space Agency (ESA) is arranging its bi-annual SpacE FPGA User Workshop at ESTEC in Noordwijk (NL) in the middle of March, and Bitvis (CGI) will present the new functionality of the open source UVVM (The Universal VHDL Verification Methodology).

This new functionality has been developed in cooperation with ESA - in an ESA project - and will significantly improve FPGA design quality while at the same reduce verification workload considerably.

The title of the presentation is 'UVVM usage is exploding. A brief introduction and all the new stuff for this standardised VHDL verification methodology'. Look here for abstract.

A UVVM course 'Advanced VHDL Verification – Made simple' will be arranged in Berlin 5-7 May.

For more information on UVVM - see this previous posts: https://www.dhirubhai.net/in/espentallaksen/detail/recent-activity/posts/