UVVM - Bringing UVM to VHDL

Tomorrow (Thursday 3 March) I will be presenting 'UVVM - Bringing UVM to VHDL'. See DVCon U.S. program and info on my presentation.

Here is the abstract: The UVVM (Universal VHDL Verification Methodology) is the fastest growing FPGA verification methodology – independent of language. This is due to the improvement UVVM yields in both FPGA quality and development time. This open source Library and Methodology has the most extensive VHDL verification support available and lets you verify really complex DUTs in a very efficient manner providing modularity, reusability, constrained-random stimulus and functional coverage similar to UVM. UVVM also has the largest library of open source VHDL verification models and components. With more than 50% of all FPGA designers using VHDL, UVVM provides a great verification solution for these users. This Workshop will provide an introduction to UVVM and get you started using UVVM on your next (or current) project.

UVVM provides a lot of the functionality of UVM to VHDL users, but as a logical evolution on VHDL rather than an abrupt switch to SystemVerilog and UVM, - and thus with a low user threshold. UVVM will in fact be a better choice for VHDL designers for a huge majority of projects, and if you are considering moving to UVM, then UVVM could be your logical first step.

I'm looking forward to present this tomorrow and answer all your questions afterwards :-)