UVVM – Brand new features, from the world's #1 VHDL Verification Methodology

Only one week left now until FPGA Verification Day 2021 and my presentation there on UVVM.

Presentation abstract:

'A good verification methodology could significantly reduce FPGA and ASIC development time. UVVM is making this much easier through the provided Testbench Infrastructure, the architecture, the BFMs and the VVCs. This presentation will briefly mention these benefits but will focus on brand new functionality to be released very soon.

This functionality is being developed in the current ESA UVVM project and has so far not been mentioned in any previous UVVM presentation.'

ESA is helping the European FPGA community

Over the last few years ESA and NRS (the Norwegian Space Agency) have invested in a significant project to extend the UVVM functionality even further, and the results from this project has been met with great enthusiasm among FPGA designers, allowing their testbenches to be better and more reusable than ever. This way ESA and NRS have made a major contribution to the European FPGA community and thus also the European electronics industry.

The new UVVM functionality to be presented here has been developed in an ESA UVVM project in tight cooperation with technical staff at ESA.

See also '2020 A great year for the Universal VHDL Verification Methodology'

Looking forward to "see you" at FPGA Verification Day next Thursday :-)

We might present some other good news there as well...