Using "export" to extend visibility of package components to enclosing package

Idea is very simple, however I haven't seen it being used so much, hence the need to share here.

Let's consider standard UVM environment hierarchy: Top level environment containing block level environments. Each block level environment contains standard UVM components, interface agents etc. Package imports reflect this hierarchy:

package apb_pkg;
  `include "apb_config.sv"
  .
  . 
  .
endpackage        

package block_level_pkg;
  import apb_pkg::*;
  .
  .
  .
  `include "block_env.sv"
endpackage        

package top_level_pkg;
  import block_level_pkg::*;
  .
  .
  .
  `include "top_env.sv"
endpackage        

Here it's important to recall that Systemverilog package imports are not recursive, meaning that declarations imported into a package are not visible by way of subsequent imports of that package. In this example, apb_config is visible by block level package members, but not by top level package members. This is not an issue in most of the cases, because there is no need for such deep visibility. However, there are some exceptions. For example, top level environment may need to use apb_config object. In that case, top level package needs explicit import of apb_pkg. Because of this, top level packages can become long, with many imported items actually low level items re-imported in top level package.

Alternative solution is to extend apb_config visibility one level up, by exporting it at a place of first import. For example, our block level package would look like this:

package block_level_pkg;
  import apb_pkg::*;
  export apb_pkg::apb_config;
  .
  .
  .
  `include "block_env.sv"
endpackage        

Export basically means: Make this visible to whoever imports enclosing packet.

Now, after apb_config is visible and ready to use in top level package, without need to explicitly import it again.