USB in Depth - xHCI

Following my posts about USB in Depth, a user ask to talk about xHCI (eXtensible Host Controller Interface) and this post is all about that.

As always, there is no way that i can talk about each item in xHCI, but i`ll try my best to be able give an north to help in your research.

I'm considering that you have read my others articles about the USB Architecture, if isn't the case, please check this, physical layer, protocol layer, framework layer .

In terms of USB Standards, xHCI will be implemented in the Host side of the usb communication, from the Endpoint to the software driver.

Have in mind that, we are in the Host side of an USB 3.x version (With "SuperSpeed") but still compatible with USB 2.x and 1.x. The xHCI was created to replace OHCI, UHCI and EHCI. Other important thing is that, all host controllers need to implement hub functions, all theses things i don't cover in my last articles, and i'll not cover in this, if you want, leave a comment and i'll cover theses topics, this topic is created due a comment!

Another point is that in USB3.x you have a PIPE interface too instead of only UTMI+.

The first point you need to consider is the Endpoint, i talked a little about Endpoint in the others articles, here and here. Everything from the pins until the Endpoint it's valid and the same here. But there is a new "player" the "Rings", and there is three of them: Transfer Ring, Event Ring and Command Ring and each Endpoint has his Transfer Ring.

Another new concept is Transfer Request Block, that is a data structure contruct in memory by the software to transfer a single physically block of data between host memory and the Host Controller. Contain a single data buffer pointer, size of the buffer and some additional control information.

Same new concepts are, Device Contexts and the Device Context Base Address Array. The Device Context is used to report the device configuration and state information to the system software and consists of 32 data structures ( index = 0 for Slot Context and the remaining (1 to 31 are Endpoints Context). The Device Context Base Addres Array is the based lookup table for accessing the Device Context in each slot.

I'll focus in the data transfer so, i'll not cover Event Ring Segmented Table, Event Ring, Command Ring. Other thing considering in the standard is an PCI config space, but i'll not cover, is away out of this scope.

Other thing to consider is the registers of the xHCI, they are:

• Doorbell Array - The Doorbell Array (up to 256 Registers of 32 Bits) is defined in the array for each Device Slot. System Software utilizes theses registers to notify the Host Controller that it has Device Slot related work for the Host Controller to perform.
• Runtime Registers - Is referred as Runtime Base too, and each register multiples of 32 bits in length, is used to control microframe and interruptions.
• xHCI Extended Capabilities - If the Host Controller implements any extended capabilities, it specifies a non-zero value in the xHCI Extended Capabilities Pointer field
• Operational Registers - The Operational Registers, referred as Operational Base, are registers to support the operation of the USB xHC.
• Capability Registers - This registers specify the limits and capabilities of the host controller implementation

In the next article i'll talk about the operation of xHCI.

If you want that i cover any topic, leave a comment!