Unleashing the Power of Collaboration: The Key to Unlocking World-Class Analog IPs

Unleashing the Power of Collaboration: The Key to Unlocking World-Class Analog IPs

Introduction

Analog IP development is a complex endeavor that requires the expertise and collaboration of multiple teams. Effective collaboration among design, verification, and other stakeholders is essential for achieving world-class analog IPs. ?

The Importance of Collaboration

In today's fast-paced semiconductor industry, collaboration is more critical than ever. Advanced process nodes are increasingly susceptible to reliability and second-order effects, demanding closer partnerships between teams. Additionally, the need to double IP speed every five years necessitates a collaborative approach to address the challenges of performance, power, and area optimization. ?

Key Areas of Collaboration

1. Circuit Design and Mask Design:

The traditional vendor-customer relationship between circuit and mask design teams has evolved into a partnership of equals. Close collaboration is crucial for optimizing floorplan and IP execution, achieving silicon performance targets, reducing die size, and ensuring silicon reliability. ?

o?? Floorplan and IP execution: The most critical path in analog IP development is analog design and mask design. The ability of analog IP time to market depends upon how well circuit/LAY team works together. The circuit/Mask design is an iterative process and this needs close partnership for success

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o?? Silicon Performance: Roughly, the Analog circuit works at 4X of speed (or even more) compared to digital. So, in order to achieve the performance, circuit and LAYOUT engineers needs to sit together, and come up with best layout with lowest parasitic to hit the performance. In the absence of this teamwork, either the design will not meet the required performance or it will take longer time to hit the performance which is a problem for Time to Market (TTM) of product

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o?? Die Size Reduction: Analog part of the analog IP takes roughly 75% of the IP area, and mostly it is modular. So, the analog design has highest potential to reduce IP area. For this goal, it is essential for Mask Design to work with circuit DE, come up with different options of the design to give best Area.

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o?? Silicon Reliability: The different second order effects such as EM/IR/EOS/ageing causes the mask design to change. To come up with the best design that has most optimum trade off between reliability and performance, circuit DE and mask designer partnership is important.

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1. Analog Design and Logic Design:

This partnership is vital for improving quality, achieving bug-free silicon, and meeting IP specifications. Collaboration in this area helps identify and address bugs at the analog-digital interface, mitigate the impact of process variation, and optimize performance and power. ?

·???????? Bug Free silicon: The area that is high prone for bug is interface between analog and digital. The reason for this area to be high prone for bugs, is that, the realization of the bugs is sometimes electrical and it is hard to find out though OVM/UVM based verification. And hence, the close partnership between Analog and Logic team would flush out the bugs through different methods of validation

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·???????? Achieving the higher performance: The process variation in advance process nodes is a major problem in the analog IP. The ability to design the analog circuits, at slower corner and make it meet power spec at fast corner is a challenge. This challenge in analog design is solved by logic FSM that trains the analog circuits per part. Such kind of analog circuit training ensures analog meets the performance, power and area of the IP. This has been major enabler for high speed IP(s) these days.

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1. Design and Verification:

This partnership is crucial for achieving zero-defect silicon. Continuous collaboration throughout the development cycle, from technology readiness to tape-out and beyond, is essential for hitting the schedule, ensuring verification quality, and identifying and debugging potential issues. ?

·???????? Hitting the Schedule: The logic DE and verification DE needs to work together on verification coverage, debug, and strategy. In order to meet the verification quality of verification (QOV), it is essential to debug the verification failure in time. So, unless this partnership happens on daily basis, analog IP cant meet the tape out schedule.

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·???????? Silicon Quality: Verification team alone cant meet the verif quality. Logic team needs to assist them on identifying the right tests and seed to improve coverage, identify different tests for UVM/OVM verification, AMS verification, formal Verification and Emulation. Without such kind of knowledge-based decision- it is not feasible to achieve bug free silicon

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1. Physical Design and SOC Team:

The physical design team plays a critical role in integrating the analog IP into the SOC. Collaboration with the SOC team is essential for customizing the IP to meet SOC requirements, ensuring seamless IP integration, and optimizing the overall system performance. ?

·???????? Customizing the IP for SOC:? The SOC has its expectation rom IP team on physical and logic aspect. Physically, SOC needs IP to meet the size, dimensions, orientation, pins, clocking, bumpout and power grid. If the IP team works with SOC from day1, it is possible to deliver the IP the way SOC wants. This definitely improves SOC execution cycle as well as IP value for SOC. Ultimately, this improves IP and SOC team’s ability to hit TTM schedule

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·???????? Seamless IP integration: Physical design team can continue partnership with SOC team on IP collateral integration, and feedback. Through constant feedback from SOC team, physical design team can improve IP collaterals quality in such a way that IP integration would be seamless at the end. This also helps SOC to improve TTM

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1. Design, Firmware, and Post-Silicon Team:

This partnership has the potential to improve product value and reduce post-launch bugs. Collaboration in this area helps identify and address silicon and platform issues, improve product quality, and enable the productization of higher-spec products. ?

·???????? Improve Product Value:? It is possible to find out the robust workaround for the proven silicon, platform issues. This avoids the stepping and saves $$$ for product. Additionally, this improves the time to market which again improves the revenue of the product. Many times, this partnership also had resulted into making the uncommitted higher spec productize through experimentation in post-Silicon.

·???????? Reduce the Post-Launch bugs possibility (Quality): The last function that is a gate before product is launched is post-Silicon. This is a crucial function for uncovering the bugs. It is essential for Design/FW/Post-SI teams work together on implementing the post-Si validation plan, debug every single silicon abnormalities, create a solid workaround around silicon issues and ensure that the quality of the product being shipped is bullet proof

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Summary

This article highlighted the crucial role of inter-functional collaboration in developing world-class analog IPs. By fostering strong partnerships between teams, companies can unlock significant benefits, including improved IP performance, faster time-to-market, and reduced development costs. Embracing a collaborative approach is essential for driving innovation and success in the competitive semiconductor industry. ?

Disclaimer:

It should be noted that the article covers inter-function partnership areas and cannot be used as a definitive playbook for Analog IP development. The information shared is based on personal experience and discussions with industry experts and should not be attributed to any past or present employers. ?