Types of Assertion
Assertion #2

Types of Assertion

In this article, we are going to discuss the Types of Assertion.

There are two types of assertion, They are

1) Immediate Assertion 2) Concurrent Assertion

Let's Discuss each Each type with an example:

Immediate Assertion :

The Assertion Check happens immediately and is completed in 0 time. For that Check, there is no time Involved.

These are used to check conditions at the current time.

These are non-temporal checks i.e. the checks are not performed across time or Clock cycles.

These are used inside a procedural Block such as (initial/always/task and function).

The Assertion failure will happen when the Expression evaluates 0, X or Z.

the assertion Check which we write using Assert() without a property, is mostly the immediate assertion. as checks happen in 0 time.

The syntax of the Immediate assertion is:

Label : assert(expression) [pass Statement]; else [Fail Statement];

Simple Syntax : assert(expression);

In case: if the fail statement is not provided and the Assertion fails. then in that case the Error is Reported during the run time.

Ex: assert(s.randomize());

it will print an error if the randomization fails, will save so much time that the Simulation is not as Expected because of randomization failure.

Another Example :

The state machine should go to Idle state only if the is_pend is low

always @(posedge clk) begin

if(state == idle) begin

assert(!is_pend) $info("TRUE: idle when no pending transaction");

else $error("FALSE: idle when there is pending transaction");

end

end

Concurrent Assertion :

These assertions test for a sequence of events and spread over multiple clock cycles i.e. they are Temporal in nature.

property keyword is used to define that the assertion is concurrent.

property is used to define a design specification that needs to be verified

They are called concurrent because they occur in parallel with other design blocks.

Syntax :

[Label] : assert property (property_name) [pass_statement]; else [fail statement];

Will understand this with a generic Sequence. The sequence is

the Acknowledge Signal needs to be asserted 2 clk after the Request signal in other words, when the Req is asserted then the Ack needs to be asserted exactly after 2 clock cycles.

Here the Checks need to happen over a period of 2 clock cycle from the Req signal becomes High, so we need to use the Concurrent assertion by Defining th e Keyword property.

Here is the Assertion Code for the above scenario:

property req_ack;                                                                                                                                             @ (posedge clk) req ##2 ack;                                                                           endproperty
assert property(req_ack) else $error("req_ack property violated");        

Your support, through likes and reposts, will encourage further exploration and engagement in meaningful discussions. Let's embark on this journey together and unlock the full potential of SystemVerilog Assertions!

Thank you for your support! ????



AsFigo AI Mahesh

AsFigo Technologies

3 个月

> (posedge clk) req ##2 ack; Why that fails in t1 (starting clock tick t0)? Also don't you need req |-> instead of ## to begin with?

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mohamed irsath I

Design Verification Engineer

10 个月

Thanks Santoshkumar Yandam for resharing

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mohamed irsath I

Design Verification Engineer

10 个月

Thanks for Reposting...?? Shanker saikrupapa

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