Towards Low-Latency FFT Hardware Architectures

One of the key topics in which we are working nowadays is the design of low-latency FFTs. This is an area that has barely been developed in the literature but, now, with the low-latency needs of digital communication, it becomes a key topic in our field.

The first work that we have proposed in this area is explained in the following journal paper, which appears in the IEEE Transactions on Circuits and Systems I this month of October:

Z. Kaya and M. Garrido, "Low-Latency 64-Parallel 4096-Point Memory-Based FFT for 6G," in IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 70, no. 10, pp. 4004-4014, Oct. 2023.

The paper is an excellent work by Zeynep Kaya where she expands the parallelization in memory-based architectures, being the first time that a parallelization of 64 branches is achieved in this type of architectures. This high parallelization leads to a fast computation of the FFT that results in a 4096-point FFT architecture that carries out the calculations on an FPGA in only 2.7 us.

As usual, the paper is available as Open Access from IEEE Xplore. Additionally, we provide the code of the implementation in our GitLab repository FFTcores.

Our next steps towards low-latency FFTs will be to reduce the latency in other types of FFT architectures, as well as to provide new architectures specifically designed for low latency.

For companies that are interested in low-latency FFT architectures, it is the right time to contact us, as we expect to protect some of our desings with patents.

Our work on low-latency FFTs is carried out in the frame of the project "RAFFTING: Realizing Advanced FFT Implementations for 6G", PID2021-126991NA-I00, funded by the Spanish Ministry of Science and Innovation, the AEI, and the European Regional Development Fund through the call "Proyectos de Generación de Conocimiento, 2021".