Tokyo FDSOI Day 2: What Sony, Samsung & Cadence Said

Day 2 of the recent SOI Workshop in Tokyo was dedicated to the “Convergence of IoT, Automotive through Connectivity”. Many of the presentations are now posted and freely available on the SOI Consortium website – click here to see the full list.

It was a really full day, so the recap in this post covers about half of the Day 2 presentations. My next post will cover the rest of them. (In case you missed it, Day 1 was covered in my previous post – you can read it here.)

Another Sony GPS Win!

The day kicked off with a talk by Sony GM Kenichi Nakano, entitled Sony Semiconductor Low-Power IoT Solution. He reminded the audience that Sony started looking at FD-SOI in 2013, and announced at ISSCC last year (the paper’s available from the IEEE – click here). Power, he said, is everything.

And that low-power GPS in Casio’s latest Pro Trek Smart watch, the WSD-F20? It’s based on Sony’s new CXD5602 – and that’s on FD-SOI, to which they give largely give credit for the >75% reduction in power from the previous generation.

Samsung: Surf’s Up!

FD-SOI is mature, and they’re ready to surf it, said Principle Designer at Samsung Foundry Marketing, Yongjoo Jeon. But, he added, they’ll continue to evolve it.

Covering a wide range of applications, he sees FD-SOI as a key in the 4th industrial revolution. In terms of power/performance, the “…excellent short channel effect enables better performance and lower power than bulk technology.” And, “Body bias enhances further performance [FBB – forward body bias] and power reduction [RBB – reverse body bias].”

That provides some unique benefits, he pointed out.

• in automotive, it’s safety: the physical dielectric isolation is almost free from SER (soft error rate)
• for analog/RF, the long channel gain is more significant with excellent noise immunity
• for every application, lower doping enhances variation immunity

Samsung reached high yield (defect density D0<0.2) very quickly, and ramped rapidly to mass production (which is where they are with NXP as of Q1/17). This, he said, shows the maturity of their 28FDS FD-SOI technology.

Then he turned to design. Samsung (which does btw, offer Design Services) has an IP portfolio that is wide and deep, with a strong, well-established reference flow, supported by both Cadence and Synopsys.

In terms of RF, 28FDS has better fT than 28nm bulk. The physical isolation of the SOI structures enables a “no guard ring” approach, and specific RF offerings include LDMOS for PAs (power amplifiers). Samsung is supporting a new mm-Wave Pcell, which will be added in the V1.1 PDK.

Samsung is also adding eMRAM (embedded magnetoresistive RAM – it’s already yielding at 60%), as they see 28nm is probably the last node for eflash. “We’re very proud of these technologies,” he said.

Samsung’s next generation of FD-SOI will be 18nm, which provides a 20% increase in performance, a 40% decrease in power, and a 30% reduction in logic area.

Cadence EDA & IP Update

FD-SOI enablement usually means PDKs and tech files, noted Jonathon Smith, Director of Strategic Alliances at Cadence. But for deep benefits, you need to work with the foundries on characterizing libraries, and that’s just what Cadence is doing with both Samsung and GlobalFoundries, he said.

He gave a very frank and interesting talk entitled Enabling an Interconnected Digital World: Cadence EDA & IP Update. IoT, he noted, will include a lot of mixed-signal and complex packaging. Customers need modular reference flows, and they want flexibility and multiple foundry nodes. For FD-SOI, Cadence has been working on PDK enablement, tool readiness and design tools for several years. There is one database for both digital and analog.

For Samsung’s 28FDS, everything from logic synthesis to sign-off and analog tools are certified. In fact Cadence recently announced its custom/analog tools and full-flow digital and signoff tools have achieved Samsung certification for the PDK and foundation library (see the press release here).

For GlobalFoundries 22FDX, Cadence is certified across the entire design flow, and the reference flows are downloadable.

In terms of IP, he acknowledged that what Cadence has is not very extensive, so they are working with both partners and competitors. However, he did point out that their Tensilica IP for automotive is gaining traction: it is used in the Dreamchip ADAS chip fabbed on GF’s 22FDX, for example.

Wait, There’s More!

Day 2 in Tokyo was really packed with excellent presentations – too much for just one post.  Watch for Part 2 of my Day 2 coverage (posting shortly) for highlights from Leti, GlobalFoundries, Soitec, MIPS/Imagination and more.

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Note: this article was first published in Advanced Substrate News on the SOI Consortium website. Click here to read it there.