TLU+ File

Introduction

Net- A wire connecting pins of each standard cell to another one is known as the net.?

Net delay, what does it mean??

The timing interconnect delay between the driver pin and load pin is known as a net delay.

Total delay = Cell delay + Net delay

Net delay (τ) = ∑ (R net . C)

overcome

TLU+ file is the right location to have a look on net delay details. which contains only the complete details of net delay in the forms of combined Resistance and Capacitance. Table Look Up is an expansion for this file and these files are with the extraction of? “.tluplus”.

These files are in the format of Binary, Which makes humans unreadable.

There are several factors which affect net parasitic:

• Net Length
• Net cross-sectional area
• Resistivity of material used for metal layers (Aluminum vs. copper)
• Number of via traversed by the net
• Proximity to other nets (crosstalk)

Interconnect introduces capacitive, resistive and inductive parasites. All three have multiple effects on the circuit behavior.

1. Interconnect parasites cause an increase in propagation delay (i.e. it slows down working speed)
2. Interconnect parasites increase energy dissipation and affect the power distribution.
3. Interconnect parasites introduce extra noise sources, which affect reliability of the circuit. (Signal Integrity effects)

How is Capacitance introduced here?

As technology nodes shrink (scaling), to minimize resistance of the wires, it is desirable to keep the cross section of the wire (W x H) as large as possible. But this increases the area. Small values of W lead to denser wiring and less area overhead. In the advanced process W/H ratio has reduced below unity. Under such circumstances the parallel plate capacitance model becomes inaccurate. The capacitance between the sidewall of the wires and substrate called fringing capacitance can no longer be ignored and contributes to the overall capacitance.

Interwire capacitance becomes the dominant? factor? ? ? in ? ? multilayer interconnect structures. These floating capacitors (not connected to substrate or ground) form a source of noise (cross talk). This effect is more pronounced for wires in the higher interconnect layer, as these are farther away from the substrate.

How is the Resistance introduced here?

At very high frequencies “skin effect” comes into play such that the resistance becomes frequency dependent. High frequency currents tend to flow primarily on the surface of a conductor, with the current density falling off exponentially with depth into the conductor.

Skin effect is only an issue for wider wires. Since clocks tend to carry the highest frequency signals on a chip and are also fairly wide to limit resistance, the skin effect is likely to have its first impact on these lines.

Net delay is calculated using Rs and Cs by some of the models, Which are

• Lumped RC Model
• Elmore Delay Model
• Distributed RC model
• Transmission Line Model
• Wire Load Models

LUMPED RC MODEL

As long as the resistive component of the wire is small, and switching frequencies are in the low to medium range, it is meaningful to consider only the capacitive component of the wire, and to lump the distributed capacitance into a single capacitance.

If wire length is more than a few millimeters, the lumped capacitance model is inadequate and a resistive capacitive model has to be adopted.

In the lumped RC model the total resistance of each wire segment is lumped into one single R, combining the global capacitive into single capacitor C.

Analysis of a network with a larger number of R and C becomes complex as the network contains many time constants (zeroes and poles). The Elmore delay model overcomes such problems.

ELMORE DELAY MODEL

Properties of the network:

• Has single input node
• All the capacitors are between a node and ground.
• Network does not contain any resistive loops.

“Path resistance” is the resistance from the source node to any other node.

“Shared path resistance” is the resistance shared among the paths from the source node to any other two nodes.

GENERAL EXPRESSION:

τdi=R1C1+(R1+R2)C2+……..+(R1+R2+R3+…..+Ri)Ci

Conclusion

TLU+ file is not an 100% accurate one but nearly all the industries are using these files as a feed to their tools for process.

Name: Harish K

Mail id: [email protected]