TLM for Image Applications

A System on a chip comprises processors, timers, interrupt controllers, buses, memories and all along that a piece of embedded software; which is embedded in a hardware device and enables all of these to work. It acts as an operating system for the complete SOC.Virtual platforms provide increased system visibility, which enables the developer to more simply isolate and debug IPC problems. System Designers and embedded software developers are accepting that SystemC Transaction level models play a key role in different phases of SOC design cycle because of its many folds benefits like architecture models, golden reference models for functional verification, early availability to act as Virtual Prototype for image quality analysis and close loop validations.

 The flow for any System-on-a-chip (SoC) is:

    I.           Architecture Definition and Algorithms development using C or MatLab

   II.           IPs design

 III.           SOC Integration

 IV.           Functional Verification

   V.           Physical Implementation

 VI.           FPGA Prototyping

VII.           Firmware and SW Development

VIII.           Silicon Validation and Engineering.

 At Imaging with each new project and new developments current design flow focuses first on RTL implementation and verification. It takes nearly 70% of total project duration to validate RTL for the device and FPGA prototype board cannot be made available unless RTL is mature enough.

 Firmware team is very much dependent upon FPGA prototype board for their developments to get started because of slow simulation speed on RTL simulation environments. Missing HW/SW co development puts lot of pressure on firmware team and delay overall project design cycle.

 Even if firmware team validates their firmware on FPGA prototype board, they are unable to validate it against real scenarios for some specific close loop algorithms. Register specifications are primary input for firmware team; they may change during RTL implementation, thus delays firmware early developments and analysis.

 The task of Image Signal Processor (ISP) is to process the data into good quality image conforming to a standard format (YUV or RGB) after streaming bayer data from sensor. It contains IPs for sensor defect correction, noise removal, bayer to rgb conversion and converting image data to YUV or RGB format according to output format expected by device.

 Different Statistics IPs gather stat information from input image like auto focus, auto exposure, white balancing etc which are being used by Firmware for image quality enhancement. The SOC Level SystemC TLM to act as virtual prototype for Firmware development.

 TLM device server-client methodology enables integration of real CMOS sensor with TLM model for real time verification of image processing firmware. TLM device is a set of libraries and programs to communicate between CMOS sensor & TLM platform and process live streamed images from sensor.  The connection is based on socket communication to enable TLM device servers to be located any where on the network. The only tools required to develop such TLM IPs are the free of- charge open source SystemC 2.0 kernel, C++, GNU compiler & gdb debugger.

 TLM platform is composed of TLM wrapper of Instruction Set Simulator (ISS) Model of Micro Processor,TLM device Sensor Application (Interface for connecting HW CMOS Sensor with ISP TLM Platform),SystemC TLM wrapper of Image Processing Algorithm IPs like sensor defect removal, noise removal, color interpolation and output formatter with their bit true C models plugged inside, SystemC TLM wrapper of Image Statistics Algorithm IPs with bit true C model plugged inside, SystemC TLM Models of I2C, SMIA Receiver, Interrupt Controller, DMA and Memory,TLM device Graphical Display Device (Interface for RGB/YUV image coming from ISP TLM platform for displaying on connected machine)

 1. Following APIs have been implemented for TLM device communication:

 int Get_Image_Data (const char * image_data_ptr, int_32* size)

void Read_Sensor_Register (int_32 address, int_32 * data)

void Write_Sensor_Register (int_32 address, int_32 data)

void Send_Image_Data (const char * image_data_ptr, int_32 size)

 2. Transaction Accurate Channel is instantiated in the platform as follows:

 TAC_CHANNEL = new tac_router< GLOBAL_ADDRESS_TYPE, GLOBAL_DATA_TYPE > ("TAC_CHANNEL", "ADDRESS_MAP");

 Data type is used to make implementation according to user defined implementation of channel for his needs.

 3. Each Block is modeled as a SystemC Module, instantiated in the main function and connected through TAC Channel

 MASTER = new tac_Cpu_iss_wrapper <tlm_uint32_t,tlm_uint32_t>("Cpu_api", embedded_software_path, debugger string, 100);

ISP_INST = new isp("ISP_ INST");

RX =new rx (“RX”);

DISPLAY = new display (“DISPLAY”);

I2C = new i2c (“I2C_SENSOR_COMM”);

MEMORY= new memory(“MEMORY”,MEMSIZE,MEMB ASE);

DMA = new dma (“DMA”);

MASTER->initiator port (TAC_CHANNEL->target_port);

TAC_CHANNEL->initiator_ port (ISP_INST->target_port);

TAC_CHANNEL->initiator_port (RX->target_port);

TAC_CHANNEL->initiator_port (I2C->target_port);

TAC_CHANNEL->initiator_port (DMA->target_port);

TAC_CHANNEL->initiator_port (MEMORY->target_port);

TAC_CHANNEL->initiator_port (DISPLAY->target_port);

4. Similarly Other IPs can be connected. Below is couple of commands which are being used for read/write primitives:

 MASTER->initiator_port.write (ADDR, DATA);

 5. Read a Block of data from Memory

 DMA.read (addr,BLOCK_SIZE);