Test Plan for 32-Deep Asynchronous FIFO

Objective

To ensure the asynchronous FIFO operates correctly under various conditions, including different clock frequencies, edge cases, and stress scenarios, while maintaining data integrity across clock domains.

FIFO Specifications

Signals:

·???????? wr_clk: Write clock

·???????? rd_clk: Read clock

·???????? rst_n: Active-low reset (assumed synchronous to both clocks for simplicity)

·???????? wr_en: Write enable (active on wr_clk)

·???????? rd_en: Read enable (active on rd_clk)

·???????? data_in: Write data (e.g., 8-bit wide)

·???????? data_out: Read data (e.g., 8-bit wide)

·???????? full: FIFO full flag (in wr_clk domain)

·???????? empty: FIFO empty flag (in rd_clk domain)

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Parameters:

·???????? Depth: 32 entries

·???????? Data width: 8 bits

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Behavior:

·???????? Writes occur on posedge wr_clk when wr_en is high and full is low.

·???????? Reads occur on posedge rd_clk when rd_en is high and empty is low.

·???????? Reset clears the FIFO to empty state.

·???????? Flags (full, empty) are synchronized across clock domains.

Test Cases

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Reset Behavior

·???????? Objective: Verify FIFO initializes correctly after reset in both clock domains.

·???????? Stimulus: Assert rst_n = 0 for a few cycles of both wr_clk and rd_clk, then deassert.

·???????? Checks:

o??? empty = 1, full = 0 post-reset in respective domains.

o??? data_out is undefined or per spec (e.g., 0x00).

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·???????? Coverage: Reset with both clocks active, one clock stopped.

Basic Write and Read

• Objective: Confirm single write and read across clock domains.
• Stimulus: Write one data item (e.g., 0xAA) on wr_clk with wr_en = 1. Read it on rd_clk with rd_en = 1.
• Checks: empty goes low after write (after synchronization delay). data_out = 0xAA matches data_in after read. empty goes high after read.
• Coverage: Single write/read with wr_clk faster/slower than rd_clk.

Fill to Full

·???????? Objective: Ensure FIFO signals full correctly when 32 entries are written.

·???????? Stimulus: Write 32 unique data items (e.g., 0x00 to 0x1F) on wr_clk.

·???????? Checks:

o??? full asserts after 32nd write.

o??? empty remains low until reads begin.

o??? 33rd write is ignored (no overwrite).

·???????? Coverage: Full condition with varying wr_clk/rd_clk ratios

Empty After Full Read

• Objective: Verify FIFO empties correctly after reading all 32 entries.
• Stimulus: Fill FIFO with 32 writes. Read all 32 entries on rd_clk.
• Checks: empty asserts after 32nd read. full deasserts after first read. Read data matches written data in FIFO order.
• Coverage: Full-to-empty transition, CDC latency.

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Random Write/Read Patterns

·???????? Objective: Test mixed operations with asynchronous clocks.

·???????? Stimulus: Randomly assert wr_en and rd_en with varying data and clock frequencies.

·???????? Checks:

o??? Data integrity across domains.

o??? full/empty flags update correctly with CDC delays.

·???????? Coverage: Random occupancy (0–32), clock frequency variations.

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Simultaneous Write and Read

• Objective: Verify behavior with concurrent writes and reads.
• Stimulus: Fill FIFO to half (16 entries). Perform simultaneous writes and reads with different wr_clk/rd_clk rates.
• Checks: Occupancy adjusts correctly (write adds, read removes). No data loss or corruption. Flags remain consistent.
• Coverage: Write/read overlap, metastable edge cases.

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Boundary Conditions

• Objective: Test edge cases at full and empty states.
• Stimulus: Write when full = 1. Read when empty = 1.
• Checks: Write to full FIFO is ignored. Read from empty FIFO returns undefined or holds last value (per spec).
• Coverage: Overwrite/underflow attempts.

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Clock Frequency Extremes

• Objective: Ensure functionality with significant clock differences.
• Stimulus: wr_clk much faster than rd_clk (e.g., 100 MHz vs. 1 MHz). rd_clk much faster than wr_clk.
• Checks: Data crosses domains without loss. Flags reflect state accurately despite frequency mismatch.
• Coverage: Wide clock frequency ratios.

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Reset During Operation

• Objective: Verify reset mid-operation across domains.
• Stimulus: Fill FIFO partially (e.g., 16 entries). Assert rst_n = 0 during writes or reads.
• Checks: empty = 1, full = 0 post-reset in both domains. No residual data effects.
• Coverage: Reset at various occupancy levels and clock phases.

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Stress Test

• Objective: Push FIFO to limits with high-frequency operations.
• Stimulus: Rapid, random write/read sequences over extended time with varying clock rates.
• Checks: Data integrity maintained. No flag glitches or CDC failures.
• Coverage: Long-term stability, maximum throughput.

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Metastability and CDC

• Objective: Verify robustness against clock domain crossing issues.
• Stimulus: Align write/read edges close to clock transitions (e.g., near metastable windows).
• Checks: Synchronization logic prevents data corruption or flag errors.
• Coverage: Edge alignment, CDC handshake reliability.

Verification Environment

UVM Components:

·???????? Agent: Two agents—one for write domain (wr_agent), one for read domain (rd_agent).

o??? Driver: wr_driver drives wr_en, data_in; rd_driver drives rd_en.

o??? Monitor: wr_monitor captures writes; rd_monitor captures reads, data_out, and flags.

o??? Sequencer: Generates write/read sequences.

·???????? Scoreboard:

o??? Queues writes and compares with reads, accounting for CDC delays.

o??? Checks full/empty consistency.

·???????? Sequences:

o??? Basic, random, stress, boundary, and CDC-focused sequences.

• Assertions: empty high when no data (post-reset or after 32 reads). full high when 32 entries written. No write accepted when full. No read when empty.
• Coverage Model: Functional Coverage: Occupancy: 0 to 32 entries. Transitions: empty-to-non-empty, full-to-non-full, etc. Write/read combinations across clock domains. Clock frequency ratios (e.g., 1:10, 10:1). Code Coverage: Line, toggle, FSM coverage for FIFO RTL.