Test mode constraints in netlist ECO

An automatic functional netlist ECO utilizes a reference netlist to correct any issues present in the implementation netlist. However, the presence of Design for Testability (DFT) logic in the design can complicate the setup of LEC (Logic Equivalence Checking) and ECO processes. DFT has become increasingly intricate in modern Integrated Circuit design, encompassing various components such as Automatic Test Pattern Generation (ATPG), memory Built-In Self Test (BIST), logic BIST, and boundary scan. Each of these DFT components has its unique set of control signals, and in some cases, a centralized control signal. DFT tools typically insert these control signals as registers to facilitate their control.

In Figure 1, the signal "all_test" is a centralized control signal. Additionally, the signal "TDR_SEL1" may function as an ATPG enable signal, while the signal "TDR_SEL2" may function as a Memory Built-In Self Test (MBIST) enable signal.

In the event that an implementation netlist has DFT components added by a DFT tool and requires a functional ECO, there are two possible scenarios to consider. In the first scenario (path 1 in Figure 2), the reference netlist may not contain any DFT components. In the second scenario (path 2 in Figure 2), the reference netlist may also have DFT components inserted. However, the DFT components in the reference netlist are likely to have different functionality compared to those in the implementation netlist. As such, both the reference and implementation netlists' DFT components should be disabled during the functional ECO process.

Typically, the DFT control signals are employed to choose between the original functional logic or the DFT logic through multiplexers. In Figure 3, these multiplexers select the DFT logic to drive the logic under test when the test control signal is set to one. Conversely, when the test control signal is set to zero, the original functional logic is selected to drive the logic under test. Failure to set the test control signals or setting them to incorrect values can result in the removal of either the DFT logic or the functional logic in ECO. Alternatively, it can lead to the replacement of the correct logic with incorrect logic, which can cause issues in the functionality of the overall system.

MBIST logic may be added to drive memory test pins during memory testing. However, these memory test pins should never be compared during LEC or ECO. In such scenarios, it is crucial to designate the memory test pins as ignored key points to ensure that they are not included in the comparison process.

In some instances, the DFT logic inserted is used to suppress 'X' propagation. By disabling the test control signal, the original functional paths can be utilized, allowing them to propagate through as intended.

To set the test control signals and ignore test-related key points in GOF ECO, the set_pin_constant and set_ignore_pin commands can be employed, respectively. Below is an example of a netlist ECO code:

read_library("t03.lib");
read_design("-ref", "reference.v");
read_design("-imp", "implementation.v");
set_pin_constant("all_test_reg/Q", 0);
set_pin_constant("mbist_enable_reg/Q", 0);
set_pin_constant("IDDQ", 0);
set_ignore_ouput("TEST_SO*");
set_ignore_pin("the_memory_instance/TCEN*");
fix_design;
write_verilog("eco_netlist.v");        

In conclusion, ensuring the proper setup of DFT logic is essential to the success of functional netlist ECO. This involves properly setting the test control signals and designating ignored key points, as failure to do so can result in the removal or replacement of the wrong logic, leading to issues in the functionality of the overall system.

For more detail on DFT constraint setting during netlist ECO, please visit https://nandigits.com/gof_display_doc.php?document_type=dft_constraints