Tech News: TSMC Advances into Panel-Level Advanced Packaging Technology

In response to the burgeoning demand for advanced packaging technologies driven by AI applications, 台积公司 is gearing up to introduce a breakthrough in its packaging capabilities. Reports indicate TSMC's plans to adopt Panel Level Fan-Out (PLFO) packaging, promising output capacities several times higher than current advanced packaging technologies.

Previously, industry giants like 英特尔 and Samsung Semiconductor have already made significant strides in deploying panel-level packaging and glass substrate technologies. Now, TSMC is poised to join the race, aligning its strategies with the increasing AI trends.

To achieve this, TSMC is collaborating closely with equipment and materials suppliers to develop new advanced packaging technologies. The planned shift involves using rectangular substrates for packaging, replacing conventional circular wafers. This transition is expected to enable the placement of a greater number of chipsets on a single substrate.

Insiders familiar with the matter reveal that the experimental rectangular substrates measure 510mm × 515mm, offering more than three times the usable area compared to current 12-inch circular wafers. The rectangular shape signifies reduced unused space at the edges, optimizing efficiency in chip assembly.

TSMC, renowned for its advanced chip stacking and assembly technologies using 12-inch silicon wafers, is expanding its production capabilities to meet the escalating demand. Sources indicate expansions at their factories in Taichung, Taiwan, primarily catering to 英伟达 , and in Tainan, aimed at 亚马逊 and their chip design partner, Alchip.

Chip packaging technology, once considered a relatively low-tech aspect of semiconductor manufacturing, has now emerged as critical in driving semiconductor advancements. This shift is exemplified by TSMC's innovative CoWoS technology, pivotal in enhancing the performance of AI computing chips like NVIDIA's H200 and B200 series.

For instance, CoWoS facilitates the integration of two Blackwell graphics processing units and connects them with eight HBM chips in the B200 chipset, thereby boosting data throughput and computational acceleration.

Mark Li, a semiconductor analyst at Bernstein Research, suggests that TSMC's move towards rectangular substrates is timely, given the increasing chip count requirements in AI chipsets. This strategic advancement underscores TSMC's commitment to staying ahead in semiconductor technology, poised to meet the evolving needs of AI-driven applications.

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