Tech News: Samsung's 2nm Process to Increase EUV Layers by 30%

According to a report from Korean media outlet TheElec, 三星电子 's upcoming 2nm process, set to begin mass production next year, will feature 30% more EUV lithography layers compared to its 3nm process.

Samsung first introduced EUV technology in 2018 at its 7nm logic process node. Since then, as the company transitioned to 5nm and subsequently to 3nm, the number of EUV layers or EUV process steps in Samsung's chip production has consistently increased.

The report, citing industry sources, indicates that Samsung's 2nm process will include up to 20 layers of EUV lithography. Looking further ahead, Samsung's 1.4nm process is expected to incorporate over 30 EUV layers.

In addition to logic chips, Samsung is also applying EUV technology to its DRAM production. For its sixth-generation 10nm DRAM, Samsung has utilized up to 7 EUV layers, whereas SK Hynix has used 5 EUV layers. As more chip manufacturers expand their EUV process steps, related industries such as photoresist, blank masks, and thin films are also expected to grow.

According to Samsung's previously announced process roadmap, the 2nm SF2 process will be launched in 2025. Compared to the second-generation 3GAP 3nm process, the SF2 process promises to reduce power consumption by 25% at the same computation frequency and complexity, improve computing performance by 12% at the same power consumption and complexity, and reduce chip area by 5%.

Following the SF2 process, the 2nm SF2Z process will feature optimized back-side power delivery network (BSPDN) technology. This technology places the power rails on the back of the wafer to eliminate bottlenecks between power and signal lines. Compared to the first-generation 2nm node SF2, applying BSPDN technology to SF2Z not only enhances power, performance, and area (PPA) metrics but also significantly reduces IR drop, thereby improving performance for high-performance computing (HPC) designs. SF2Z is expected to enter mass production in 2027.

Samsung has also disclosed other release dates for its 2nm processes. The SF2 and SF2P processes for mobile applications will be introduced in 2025 and 2026, respectively. The 2nm process for artificial intelligence (AI) and HPC applications is scheduled for release in 2026, preceding the BSPDN technology. Additionally, the SF2A process for automotive applications is slated for launch in 2027.

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