Tech News: Samsung Delays Sixth-Gen 10nm 1c DRAM by Six Months Due to Yield Issues

According to a recent report from South Korea, 三星电子 had previously announced that its sixth-generation 10nm-class 1c DRAM process?would be completed and ready for mass production by the end of 2024. However, due to challenges in yield performance, the development timeline has been extended by six months. As a result, the mass production of the sixth-generation HBM4, which was initially scheduled for the second half of 2024, will now be delayed until 2025.

The delays stem from difficulties Samsung encountered with its sixth-generation 10nm-class 1c DRAM process. Although the company managed to produce its first test chip by the end of 2024, it was unable to meet the expected yield targets, prompting a delay in the final development phase. Samsung aims to improve the yield to approximately 70% during the additional six-month period. Industry experts suggest that the typical development cycle for each DRAM process generation is around 18 months. Samsung's fifth-generation 10nm-class 1b DRAM process, which was developed in December 2022 and mass-produced in May 2023, had not faced similar delays.

If the yield improvement progresses as planned, the mass production of the sixth-generation 10nm-class 1c DRAM process may be pushed back to the end of 2025. This delay will also have a direct impact on Samsung's development of its HBM products, as the core DDR5 DRAM is integral to HBM4. Since HBM is derived from the DRAM process, any delay in DRAM production will inevitably affect HBM mass production timelines, pushing it into 2025 or later. This shift is significant as Samsung had initially planned to incorporate its 1c DRAM process into HBM4 and start mass production in the second half of 2025.

To address these delays, Samsung is concentrating its efforts on improving the yield of its sixth-generation 10nm-class 1c DRAM process during the first half of the year. While competitors like SK hynix have opted for a more stable approach by using the fifth-generation 10nm-class 1b DRAM process for HBM4, Samsung is committed to rapidly enhancing both performance and energy efficiency. Achieving these goals will depend heavily on the ability to expedite mass production.

As part of its strategy, Samsung is making adjustments to the design of the 1c DRAM process to further optimize its yield and ensure that the technology can meet market demands.

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