Synthesis

Synthesis is the process of converting RTL code, typically written in hardware description languages like Verilog or VHDL, into a gate-level netlist. It involves mapping the functionality specified in the RTL code to a library of standard cells, such as NAND, NOR, XOR gates, etc., provided by the target technology.

Inputs : RTL, Technology libraries, Constraints (Environment, clocks, IO delays etc.)

Outputs : Netlist , SDC, Reports etc.

Synthesis = Translation + logic Optimization + Mapping

Synthesis is a crucial step in VLSI chip design for several reasons:

1. Translation: It enables the transformation of RTL code, which captures the design's functional behavior, into a gate-level representation that can be implemented in hardware.
2. Optimization: Synthesis optimizes the design for various metrics, such as area, power consumption, and timing. By leveraging advanced algorithms, it improves the performance and efficiency of the resulting netlist.
3. Complexity Management: As chip designs grow increasingly complex, synthesis helps manage the intricacies by automatically generating the gate-level netlist.

Logical synthesis takes the RTL (register transfer level) description of a design and produces a gate-level netlist.?Logical synthesis operates at a high level of abstraction, where it is concerned with the logical functionality of the design.

Physical synthesis takes the gate-level netlist and produces a physical layout of the design. Physical synthesis operates at a lower level of abstraction, where it is concerned with the physical implementation of the design.

Synthesis Inputs

1. Register Transfer Level (RTL) : RTL can be written in many languages like Verilog, VHDL, System Verilog etc. All these languages are quite similar.
2. Timing Library (LIB): The timing library (.lib) is an ASCII representation of the Timing, Power and Area associated with the standard cells.
3. Standard/Synopsys Design Constraint (SDC): Standard design constraints or Synopsys design constraints contains the timing and power related constraints which control design w.r.t to the spec.
4. Unified Power Format (UPF): The Unified Power Format (.upf) is an IEEE standard which is used to define the power and related aspects of multi voltage design. UPF contains supply set definition, power domain definition, power switch definition, retention cell definition, level shifter cell definition and other low power related definition.
5. Physical Library (LEF):? The Physical Library or Library exchange format (LEF) is?an ASCII representation of the abstract of the standard cells. It contains all the physical information about the cells (Technology and Macro cells) and nets.
6. Design Exchanged Format (DEF): For physical synthesis DEF is a must input. This DEF contains the floorplan information of the design and it doesn’t contain the information about the objects which we have at physical design steps.
7. Other Tech files

Technology library is a collection gates along with characteristics information of it. Technology libraries are provided by fabrication house (such as TSMC, UMC etc.) based on technology of manufacturing. Thus technology libraries contain information about the characteristics and functions of each logic cell provided in a semiconductor vendor’s library.??Technology libraries are distributed and maintained by semiconductor vendors (i.e. fabrication houses).

A link library is a collection of cells that are used to describe the function of mapped cells prior to optimization. The link library is typically used to provide cells that are not available in the target library, such as RAMs, ROMs, and macros.? The link library can contain cells from any technology library, but it is typically recommended to use the same technology library for the target library and the link library.

The technology library you want to map to during synthesis. Target library is used for technology mapping. All the combo (AND, NAND, NOT, etc) and the sequential (SDFF, DFF, etc) are mapped to equivalent gates from the target. Synthesis is about converting RTL to gates.