SYNTHESIS

What is Synthesis?

It is the process of tranferring higher level of abstraction (RTL) to implementable low level of abstraction, i.e the process of tranforming RTL to gate-level netlist. design Compiler (DC) from Synopsys and RTl Compiler from Cadence are tools used for synthesis.

Goals of Synthesis

• To get a Gate-level netlist
• Inserting Clock Gates
• Logic Optimization
• Inserting DFT Logic
• Logic Equivalence between RTL and Netlist should be maintained

Synthesis Flow

Inputs and Outputs of Synthesis

Inputs:

• RTL-HDL files
• Libraries
• Constraints
• UPF

Outputs:

• Netlist
• Reports
• UPF:Unified Power Format

HDL files generation & library setup

• HDL input files are written in VHDL or verilog or system verilog
• HDL partitioning and coding style directly affect the synthesis and optimization process
• Libraries are based on the semiconductor technology used

Reading Files

There are two methods to read files to DC. One is to use analyze and elaborate commands; other is to use read_file command.

• Analyze and Elaborate -Analyze command: ~Reads HDL source files and performs HDL syntax checking and synopsys rule checking ~Check files for errors without building generic logic for the design ~Created HDL library objects in an intermediate form ~Stores the intermediate files in a location specified by define_design_lib command -Elaborate command: ~Translate the design into its GTECH representation ~Allows changing of parameter values defined in source code ~Replaces the HDL arithemetic operators in the code with design ware components ~Perform link automatically
• The read_file command~Performs the same opeartion of analyze and elaborate in one step~Doesnot create intermediate files for verilog~Creates intermediate files for VHDL~Doesnot execute the link command automatically. Link has to be manually done after read_file command~Reads several different formats viz.VHDL,Verilog,System Verilog,ddc.

Design environment Constraints

• Once the design have been read in, you need to define design environment and design constraints
• Design environment: It consists of operating conditions, wire load models and system interface requirements
• Operating conditions: It consists of process,voltage,temperature requirements. The effect each of these can have on the chip need to be considered during synthesis and timing analysis.Most libraries have default setting for opearting conditions.Operating conditions can also be explicitly specified by using set_operating_condition command.Operating conditions are set in dc_setup.tcl file using set_operating_condition command.
• Wire Load Models: It allows DC to estimate the effect of wire length and fan out on resistance, capacitance and area of nets.DC uses these values to calculate wire delays. We use zero WLM when synthesis is done using DC.
• System Interface:The information regarding outside logic driving and receiving signals from your ASIC is captured through these constraints. It consists of input drive strength (set_driving_cell) , capacitive load (set_load),etc.. . report_lib,report_design are few of the commands to see the loaded environment constraints

Timing Paths

• The timing analysis tool finds and analyses all of the timing paths in the design.Each timing path has a startpoint and an endpoint
• The startpoint of a path is a clock pin of a sequential element or an input port of the design
• The endpoint of a path is the data input pin of sequential element or output pin of the design

• Path 1 starts at input port and ends at data input pin of sequential element
• Path 2 starts at clock pin of sequential element and ends at data input pin of sequential element
• Path3 starts at clock pin of sequential element and ends at output port
• Path 4 starts at input port and ends at output port

• Static Timing Analysis is a method of validating the timing performance of a design by checking all possible paths for timing violations under worst-case conditions. Setup and Hold are most important timing checks performed.
• Setup: The time for which the data should be stable before the active edge of the clock
• Hold: The time for which the data should be stable after the active edge of the clock

Constraints

• When Design Compiler optimizes your design, it uses two types of constraints -
• Design Rule Constraints:The logic library defines these implict constraints.These constraints are required for a design to function correctly.They apply to any design that uses the library. By default,design rule constraints have a higher prority than optimization constraints
• Optimization Constraints:These are applied to the design on which you are working for the duration of the dc_shell session and represent the design's goals.During optimization, Design Compiler attempts to meet these goals, but no design rules are violated by the process. To optimize a design correctly, you must set realistic contraints.

Timing Constraints

• To accurately set up timing constraints, you need to specify the following:-Clock-I/O timing requirements-Combinational path delay requirements-Timing exceptions
• Clock: To define a clock create_clock command is used, and create_generated_clock command is used to define internally generated clock.Few specifications of clock include clock source,clock period,duty cycle,clock name etc.