Synopsys UCIe PHY IP on TSMC N3E Achieves First-Pass Silicon Success

Synopsys extends its leadership in multi-die system design and die-to-die interface technology with the world’s first silicon results for UCIe PHY IP on TSMC N3E process. Our initial Synopsys UCIe PHY IP silicon results are back from the lab, showing robust link margins and architected for data rates of 16Gb/s and scalable to 24Gb/s per channel. These results were achieved in a realistic use case showing data passing through 8 modules, each implementing 64 TX and RX lanes. The IP, supporting an advanced packaging technology, shows exceptional power efficiency of 0.3 pJ/bit.??

This achievement enables designers to confidently integrate the Synopsys UCIe PHY IP, which has been adopted by multiple customers, into their multi-die systems to accelerate their time to market.

Summary?

As more companies adopt multi-die systems to take advantage of their performance benefits, standards like UCIe are playing a key role in ensuring interoperability, reliability, robustness, and security of the die-to-die link. Synopsys’ complete UCIe IP solution, including controller, PHY, verification IP, test, and emulation, enables robust, low-latency, and secure die-to-die connectivity for high-performance computing and automotive applications. In addition, Synopsys’ UCIe link health monitoring, test and repair (MTR) controller helps to ensure reliable operation of multi-die systems during all phases of silicon lifecycle. Synopsys is an active member of the UCIe Consortium and is dedicated to helping customers jump start their multi-die system designs with our UCIe IP solution.?