Synopsys UCIe PHY IP Achieves First-Pass Silicon Success on TSMC N5 Process

新思科技 continues its commitment to customer success with UCIe PHY IP silicon on 台积公司 N5 process for standard packaging technologies. This achievement builds on the recent silicon success of the Universal Chiplet Interconnect Express (UCIe) IP on TSMC’s N3E process for advanced packaging technologies. Customers now have the flexibility to explore the packaging options and process technologies that best fits their needs. The silicon results show wide open eyes and robust die-to-die traffic at 16GT/s, scalable up to 24GT/s, with exceptional power efficiency and performance. The test chip uses 4 modules, each implementing 16 TX and RX lanes, and enables testing for various channel reaches between dies.

The new era of pervasive intelligence requires advanced innovation, closer collaboration, and expert engineering. Synopsys is driving the new era with a complete UCIe IP solution, including PHY, controller, and verification IP. The UCIe link health monitoring, test and repair (MTR) feature maximizes reliability during the multi-die system life cycle. Our successful ecosystem interoperability demonstrations deliver confidence and promote the adoption of the UCIe standard. Our engineering experts are working tirelessly to deliver UCIe IP that deliver results beyond the standard. ?