Synopsys Demonstrates World’s First UCIe IP Operating at 24G on TSMC N3E with Standard Package

Synopsys leads the semiconductor industry and mainstream adoption of multi-die systems with the third overall first-pass silicon success of the 新思科技 UCIe IP on 台积公司 ’s N3E process. Achieving silicon success on TSMC’s N3E for both standard organic and advanced packaging technologies and on N5 for standard packaging technologies places the Synopsys UCIe IP as the gold standard for die-to-die interfaces. An additional proof point is the successful interoperability between our UCIe IP on TSMC’s N3E process and Intel’s UCIe IP on Intel 3nm technology.

The diverse array of package options is driving the need for various UCIe PHY variants, each tailored with distinct floorplans, signal/power integrity considerations, etc. Synopsys’ focus on supporting multiple packaging technologies provides a seamless integration for our customers. Multiple keystone companies have adopted the Synopsys UCIe IP Solution to move their innovations forward and meet their die-to-die connectivity requirements. High bandwidth, low latency die-to-die connectivity is the lynchpin of multi-die systems which Synopsys is enabling with a complete solution, including PHY, controller, verification IP, and comprehensive tool flow utilizing Synopsys’ 3DIC Compiler. Synopsys is an active member of the UCIe Consortium, helping to develop and drive adoption of the UCIe standard.