Switch roles between IC Design Frontend (FE) and Backend (BE)

Switch roles between IC Design Frontend (FE) and Backend (BE)

This series of articles tries to summarize roles in IC design at a simple and basic level and also make clear the difference between each roles. Purpose: to help freshmen, recruiters, or someone interested in IC design resources.

More than 15 years ago, many IC design companies had only 2 main departments: FE and BE. It's straightforward to look for fresh candidates, train them, and then assign any FE/BE tasks after a short time.

But nowadays, FE has split into distinct roles, such as

+ RTL designer who writes the Hardware Description Languages (HDL) - RTL/Verilog Code to create

  • CPU design, which focuses more on performance (speed and computing) than anything else or SoC design, which focuses more on integrations
  • Analog IP (circuit/device or memory bit-cell-based), Digital design and integrations (standard cell-based) or Mixed-signal (combination of analog + digital IPs into a system)
  • Peripherals, multimedia, wireless, communication, controllers, PHY, automotive IPs and so on. See most of the silicon IPs in https://www.design-reuse.com/sip
  • ARM-based or RISC-V based sub-systems and related design tools
  • Sub-system design like clock, power, bus, analog, RF,...
  • CAD/flow/environment/quality control and assurance setup for RTL Designers

+ Design Verification: validate RTL functions working as expected

  • Modems 3G/4G/CDMA/5G
  • Mixed-signal, RF
  • Silicon IPs, CPU, clock, power, whole chip,...

+ STA: data transfer correctly with expected clock cycles

+ DFT: make sure design/chip is testable during design and also in silicon wafer/package

+ Characterization: from digital design data to real-life Resistance and Capacitance that EDA tool could use for pre-silicon validation

+ CAD or simulation environment setup & and enhancements

In the other side, BE is divided into different BE/Place and Route (PnR) roles

  • Mixed-signal/Block/Chip top PnR on balancing between Power (dynamic/static/total) and performance (fmax or frequency) and Area (congestion, route-ability) or PPA
  • CTS/Power PnR & optimization expert role
  • IP hardening & quality assurance
  • Physical Verification (PV)
  • Sign-off for IP/Block/Top Chip
  • (Advanced) Package Designer
  • PI (EMIR), thermal
  • design life-cycle analysis

And so on... such as the Product Field Application Engineer (AE) who continuously improves EDA methodologies together with their EDA R&D for all IC design phases

Why are there so many roles nowadays? Because of Moore's law, transistor/FET density is 2x higher every 2 years.

  • Chips are integrating more and more functions with the same mm2, such as moving from 7nm, 5nm, 3nm, and 2nm
  • Development of new, advanced, and complicated protocols, more functions in phones, and handheld devices, safe & and realizable requirements for automotive chips, high-performance computing systems, and smart IoT devices,...
  • Development of new IC design methodologies & EDA tool features, especially AI-related features such as CTS useful skew, advanced PPA optimization engines, DSO.ai, Cerebrus, 2.5, 3D-IC,...

Many young engineers tend to stick to one role & and evolve deeper and deeper. This makes them a technical expert faster after a few years, but it limits their ability to expand their knowledge and skills of the whole chip design. And to create the whole IP product or bring it up to the next technical management level, their knowledge will not be limited to 1 or two technical roles, it's necessary to make decisions in many phases of the Chip Design.

Have you ever experienced switching roles from/to FE to/from BE? or change roles within FE/BE such as from a PnR engineer to an R&D or CAD member, flow setup, or FAE, or even taking several roles at the same time?

Tommy Lê

Sr II Physical Design Engineer - Logic&Physical Synthesis for cutting-edge SoC

1 年

Interesting topic, I wouldn't call it "switching roles" in my case, I've been doing "traditional" DV for 6 years, and then expanding to Implementation role, I see it as a continuation of what I've learned and done in DV, stepping foot more into the Physical fields for several years now. Our chips are getting bigger and more complex faster than we can adapt to, the roles may get mingled, and someone has to step up and do the task no one in the team really knows or has done before. It's like in Football, we have the traditional Striker, Midfielder, Defender, and somewhere someone has become the CAM (center attacking midfielder) or CDM (center defending midfielder). If the organization supports expanded roles and benefits the engineer and business purpose, it happens and vice versa. Finally, for me, it's better to have more than 1 role if you plan to stay 10+ years in the industry long term. Because our design always outrun the engineer.

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