Substrate coupling. Part 4

This article is part 4 in a series. Please, make sure you read parts 1 to 3 before this one. They introduce the concepts we will build on.

Now that we have defined the coupling through shared impedance, the role of substrate in shared impedance and the equivalent schematic of a substrate, we will build a general coupling schematic.

First, we have to remind that substrate resistance couples two signals (usually supplies) together. If the coupling level is too high, the circuit may not meet its requirements.

Here is a general coupling schematic involving two cells:

Cell 1, on the left, generates in one of its supplies some variable current resulting from its activity: IActivity1. Because of its supply local internal impedance (all the series impedance from actual supply pin to cell supply pin), some variable voltage, VUndesired1 exists on Cell1 local supply.

Through the cell finite supply rejection, part of this variable voltage will be transformed in a variable current by a "PSGM" (Power Supply Conductance since it turns a voltage into a current). This current sums up with IActivity1.

This mechanism creates an undesired loop:

Of course, each cell must be able to survive its own activity. In other words, this loop must be stable. Loop stability depends on local supply impedance and cell supply trans-conductance which are both complex values depending on frequency.

By the way, this is the reason for characterizing supply rejection and for using short and wide supply lines. Bypassing capacitors help as they reduce high frequency impedance, compensating for the natural cells tendency to have poorer supply rejection at high frequencies and supply impedance tendency to increase at high frequencies because of series inductance. But it's not actually the topic here!

If an impedance (ZCoupling) couples the supplies of the two cells, the situation becomes more complex. Not only do the cells cause trouble to themselves but also to the other one. Finally, supply series impedance acts as decoupling while impedance between supplies act as coupling. This is the reason for their names in the schematic. Functionally, interactions can be represented like this:

Of course, both loops must be stable as already stated. But in addition, through PSRR (in fact Power Supply Gain...), each cell output shows an undesired signal that results from its own activity and from the other cell activity.

For a given set of activity currents, and supply rejection values, there is a criterion to satisfy on the three impedance values for two cells to operate safely. This criterion can be analyzed using small signal models, according to above schematic.

Intuitively, the lower the decoupling impedance values and the higher the coupling impedance value, the better.

Even when every other coupling impedance has been removed, the substrate remains. It can't be removed. Here we are, finally with this series of articles headline!

Of course, in real life, an IC has much more than two cells and the number of interactions to consider is large, but since they can usually considered linear (small signal model) cells can be analyzed two by two and results be superimposed.

So, in general, the goal is to achieve a substrate resistance between substrate access high enough for the interaction between cells to be low enough so that the circuit meets its specification.

What are the variables we can use to reduce parasitic coupling through substrate?

We have established that Wells define kind of shorts at substrate surface. As a start point, we will study the resistance between two PWells. Variables of influence are:

• Wells size
• Wells distance
• Wells position in chip
• Chip size
• Chip thickness
• Substrate conductivity

Why is it important to know the variables and their impact if a Field Solver such as EZMod3D can extract a substrate model that we can simulate together with the chip?

Isn't that sufficient to check that substrate coupling is acceptable for the IC target performance?

Yes, it is. But what if the substrate coupling is unacceptable?

How to modify the design and/or the layout so that substrate coupling gets within an acceptable range ?

And aren't there rules of thumb to safely design circuits that do not suffer substrate coupling above acceptable limits?

So, let's go with variables effect analysis. First, let's notice that most variables come from geometry. Only substrate conductivity is not linked to geometry.

Substrate conductivity has an obvious impact: Substrate resistance between two access is inversely proportional to substrate conductivity. But usually, substrate conductivity is not an option, it is defined by the process and we have to deal with it.

For the geometry variables there is nothing obvious we can say, not even anything intuitive. So we'll work on an example using a Field Solver, namely EZMod3D to perform the analysis and come to some conclusions.

We'll consider only two PWells in a chip and see how resistance between them depends on geometry variable. The headline picture shows one case of extracting resistance between two wells (the small red and green parallel-piped elements) inside a chip (the large black parallel-piped element).

First, let's consider a square chip 5 x 5 mm2. We'll analyze two thickness values, 250 um and 450 um. We'll extract resistance between two PWells 2 x 2 um2 1 um thick on a line crossing the chip center. Substrate resistivity is 10 ohm.cm, so its conductivity is 10 S/m. This is a very common type of substrate.

The distance between the two Wells is varied while the distances of each Well to chip center are kept identical. Here is the extracted resistance versus distance:

Note that distance varies from 2 um to 2 mm (x axis scale is log), a ratio of 1 to 1000. Resistance changes from 14.3 k-ohms to 22.4 k-ohms, a ratio of 1 to less than 2...

First point, we see that increasing the distance between two substrate access increases substrate resistance... But not much. This result should rather be taken the other way round: Reducing distance between access below some microns does reduce resistance. However, attention should be paid to the fact that at very short distances, if both NWells and PWells are used, parasitic bipolar can start playing if voltages are not set properly. As stated earlier, this effect is not considered here.

Second point, we see that substrate thickness has an impact. The thicker the substrate, the lower the resistance values, as expected. But as can be seen, more than doubling thickness decreases resistance by 12% at long distances to 15 % at short distances.

So, for given Wells sizes, neither distance nor substrate thickness can change resistance by more than a factor 2. That's only 6 dB improvement on coupling. This is usually insufficient by far. This might be a bit different for larger Wells, but probably not by so many dB.

All for now. In future posts, we'll analyze effect of Wells size, position in chip and chip size.

Again, feedback is warmly welcome. Many hundreds of persons read this series, some tens of persons react, only one so far commented... Please like, comment and share if of any interest to you or if you disagree.