Substrate coupling. Part 3

This article is Part 3 in a series. Please, make sure you read and understood the concepts from Part 1 and Part 2 before going further.

In part 1, the shared impedance coupling concept was introduced.

In part 2, parasitic coupling through substrate was introduced.

Before going further, we have to go through some theoretical considerations and their practical consequences.

In part 2, we stated that substrate equivalent schematic connects substrate access (PWells and anodes of NWell-PSub diodes) by resistors. Is that true ?

Lets consider a parallel piped volume of silicon with electrodes (Red and Green) at two opposite ends:

Let's call "L" the length (distance between electrodes) "W" the width and "T" the thickness.

Silicon substrate is made from exhibits both a conductivity and a permittivity. So, equivalent schematic of our silicon parallel piped element is a parallel R-C cell.

Lets call ε silicon absolute permittivity which does not significantly depend on doping and σ the conductivity that depends on doping type (P or N) and doping level. For a given substrate, both ε and σ are known.

Then, R and C can be calculated, time constant can be defined and finally impedance vs. frequency comes:

Behavior, of course is that of a parallel R-C cell. Here is what |Z| vs. frequency looks like for R = 1 ohm and Tau = 1 s in a log-log space.

The key point is that time constant does not depend on geometry, W, T and L cancel out when multiplying R by C.

If element was not parallel piped but had an arbitrary shape, its resistance between defined access would be proportional to resistivity and to a shape factor S. Capacitance would be proportional to permittivity and inversely proportional to the same shape factor S.

So, time constant, even for an arbitrary shaped element, depends only on resistivity and permittivity!

DC impedance obviously reduces to R term only that depends on geometry but cutoff frequency does not depend on geometry.

This means that whatever the shape and size of an homogeneous element, extracting the resistance between access is sufficient to predict its behavior over frequency.

This is a very important result that reduces the complexity of creating an homogeneous substrate model over frequency.

Another result is linked to that one: At frequencies much below cutoff, substrate behaves like a pure resistance network. At frequencies much above cutoff, it behaves like a pure capacitance network. In between, it behaves like a parallel R-C cells network.

Extracting an homogeneous substrate resistance network between the access is always sufficient. Whenever frequencies are such that C values are required, they can be computed from R values knowing the R.C product is substrate time constant defined by conductivity and permittivity. WOW!

There is still a concern: How to extract resistance value of substrate between an arbitrary shaped access ? For some particular shapes, an analytical solution exists. In most cases, extracting resistance does require a Finite Element Analysis using a Field Solver.

EZMod3D is such a tool and can be used to perform substrate extraction. It is the most cost effective tool on the market for linear substrate analysis. In addition, it is a multi-physics tool and it can do much more: 3D capacitance extraction, Thermal analysis etc...

What about this time constant and related cutoff frequency values ? Let's consider an example:

For an often used 10 ohms.cm resistivity substrate (ohm.cm is a conventional unit in this field...), conductivity is 10 S/m (just convert resistivity in ohm.m by dividing it by 100 and then invert it).

Relative permittivity of silicon is 11.9 so absolute permittivity is 11.9 times 8.854E-12 F/m or 1.053626E-10 F/m.

Then, time constant is permittivity (1.053626E-10 F/m) divided by conductivity (10 S/m) or 1.053626E-11 s

Related cutoff frequency is 15.16 GHz.

So, for a 10 ohms.cm substrate, at frequencies below 1.5 GHz or so, behavior can be described by a resistance network.

Above 150 GHz or so, it can be described by a capacitance network.

In between, an R-C cells network in required. But for any branch of the extracted equivalent schematic, R value instantly defines C value for their product to be the substrate time constant.

Now, its time to look at NWells and PWells that define the access to substrate, either directly (PWells) or through diodes (NWells).

Wells (both P and N) conductivity is usually three orders of magnitude higher than substrate conductivity. In other words, Wells regions can be considered as shorting the substrate surface, they act like contact regions, keeping in mind that for NWells, it is the anode of the isolation diode that somewhat contacts the substrate.

This is the second important simplification of substrate extraction. Of course, its validity completely depends on actual process data. However, Wells conductivity does not vary that much from process to process. For substrate, conductivity values can be as low as 66.6E-3 and as high as 2.0E6. These are values I already met, may be the range can be larger.

At the low end of conductivity range, the simplification is even more valid. No problem.

At high conductivity values, breakdown voltage would be very low and an epitaxial P layer is usually added with a conductivity around 10 S/m.

So, finally, the assumption that Wells short the substrate surface is valid in most cases.

In case substrate is not actually homogeneous, of course, each region has its own cutoff frequency than can be calculated. If operating frequencies are not much lower than lowest cutoff frequency of any substrate region, a true R-C analysis would be required, but this is rarely the case.

So far, we assumed that substrate is P type, which is the most common case. Of course, all what was said so far remains true in case of a N type substrate. One difference: The isolation diodes access substrate with their cathodes and NWells access substrate directly. That's all.

Now, what about the border between NWells and PWells ?

This is an important question because if we assume that both Wells short the substrate surface and if surface is occupied either by NWell or PWell, everything is shorted!

This is not the case, of course. In fact, the PN junctions have to be reverse or at most zero biased to keep isolation.

In both cases, a depleted region a couple microns thick exists between effective PWells shorts and NWell shorts.

This is exactly where the resistance between PWells and NWells diodes anodes is located inside substrate. Both PWells and NWells have to be sized by -0.5 to -1 μm to create the actual access to the substrate so that extracted resistance values are realistic.

Resistance values between substrate access will be the next big topic of this series. We will use EZMod3D to explore the underlying phenomenons an to define some rules of thumb that will be helpful to understand the results of substrate analysis.

Comments on this series of articles are warmly welcome. Feedback is important to drive this topic in the right direction.