State of EDA and Domain Modeling for Digital Design

The semiconductor industry is often equated to trying to build a nano-sized city on a silicon wafer. The average time to market for each product is 1.5 years.

With such an enormous task and tight timeline, it is interesting to see that the state of the CAD and EDA tools in the industry is beyond fractured and does not seem to lend itself to easy automation and continuous workflow. Take a look at the following simple front-end workflow that I have deconstructed.

No alt text provided for this image

Absolute madness.

We have one software respectively for each category of simulation, static analysis, linting, synthesis, and not to mention the archaic obsession with the esoteric knowledge of Perl and Tcl scripting when trying to glue things together. The reports generated by the tools also do not lend themselves to easy parsing. Where are the JSON/XML reports when you need them? You'll often find yourself writing awk/sed/grep scripts to do the simplest thing.

Looking at the diagram above, the typical workflow for an RTL designer, if following SCRUM, is quite complicated due to the fact that any changes in the RTL have to go through so many design tools before they could be safely merged to the codebase. If each feature is organized as a story, the process can also be potentially blocked for weeks waiting for the verification side.

Compare this to a civil engineering project where Autodesk dominates. The Autodesk CAD tool is able to do design, integration, revision, simulation as well as validation. Not only that, Autodesk is also capable of integrating with Python for easy automation and advanced simulation, allowing the engineers to leverage the enormous amount of open source libraries. Such day and night differences.

One good news is that there are already some efforts being taken by the open-source community in an attempt to fix the current conundrum caused by the opaqueness of these EDA vendors. See https://github.com/olofk/fusesoc

Personally, I have been reading books about the details of some of these EDA algorithms and might attempt to have a go at it myself, seeing that there are already some good open-source parsers on Github.

See : slang, verible and firrtl

要查看或添加评论,请登录

Alan Saw的更多文章

  • ASIC books and resources

    ASIC books and resources

    There are many excellent books about front-end ASIC design and architecture. Here are some of the few books/materials…

  • Understanding UVM

    Understanding UVM

    (Basic familiarity with SystemVerilog and OOP concepts are assumed) Let's talk about UVM. Entry-level engineers in the…

  • Why HDL needs to be further abstracted, applicative functor

    Why HDL needs to be further abstracted, applicative functor

    Suppose we want to integrate the AHB bus protocol into our sub-design. The digital design process for an…

    3 条评论

社区洞察

其他会员也浏览了