STA:

->Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations.

Why is timing analysis important when designing a chip?

=> Timing is important because just designing the chip is not enough; we need to know how fast the chip is going to run, how fast the chip is going to interact with the other chips, how fast the input reaches the output etc…Timing Analysis is a method of verifying the timing performance of a design by checking for all possible timing violations in all possible paths.

-> Timing Analysis can be done in both ways; static as well as dynamic.

Dynamic Vs Static STA

Basic Definitions:

1) Setup Time:

·???????????? Setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data are reliably sampled by the clock. This applies to synchronous circuits such as the flip-flop.?

2) Hold time:

·???????????? Hold time is the minimum amount of time the data signal should be held steady after the clock event so that the data are reliably sampled. This applies to synchronous circuits such as the flip-flop.?

3) Slack:?

·???????????? It is difference between the desired arrival times and the actual arrival time for a signal.?

·???????????? Slack time determines [for a timing path], if the design is working at the desired frequency.?

·???????????? Positive Slack indicates that the design is meeting the timing and still it can be improved.?

·???????????? Zero slack means that the design is critically working at the desired frequency.?

·???????????? Negative slack means, design has not achieved the specified timings at the specified frequency.?

4) Required time:?

The time within which data is required to arrive at some internal node of the design. Designers specify this value by setting constraints.

5) Arrival Time:?

The time in which data arrives at the internal node. It incorporates all the net and logic delays in between the reference input point and the destination node.?

?Setup Slack = Required time - Arrival time

?Hold slack = Arrival time - Required time?

• Startpoint.?The start of a timing path where data is launched by a clock edge or where the data must be available at a specific time. Every startpoint must be either an input port or a register clock pin.
• Combinational logic network.?Elements that have no memory or internal state. Combinational logic can contain AND, OR, XOR, and inverter elements, but cannot contain flip-flops, latches, registers, or RAM.
• Endpoint.?The end of a timing path where data is captured by a clock edge or where the data must be available at a specific time. Every endpoint must be either a register data input pin or an output port.

STA also considers the following types of paths for timing analysis:

• Clock path.?A path from a clock input port or cell pin, through one or more buffers or inverters, to the clock pin of a sequential element; for data setup and hold checks.
• Clock-gating path.?A path from an input port to a clock-gating element; for clock-gating setup and hold checks.
• Asynchronous path.?A path from an input port to an asynchronous set or clear pin of a sequential element; for recovery and removal checks.

#vlsi #semiconductor #sta #hardware

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