- Own SoC memory controller & PHY micro architecture including integration into SoC
- Analyze complex data flows at the subsystem and full chip level.
- Have good knowledge on The?JEDEC?memory specifications for semiconductor memory circuits and similar storage devices.
- Strong experience with using 3rd party Memory controllers and PHYs for (LP)DDR4, 5, 6 and HBM 2,3,4.
- Perform high-level performance modeling/simulation and analysis of memory controller features, applications, benchmarks, and complex uses cases
- Define performance enhancement techniques such as end to end hashing for the performance
- Work with the 3rd party IP vendors to make sure SoC power and performance targets per use cases are fully covered with their IP offering. ?
- Interact with the design partner teams to define IP integration, SoC flows to make sure SoC level targets are met.
- Work with design partner and IP teams to review Lint, CDC, SDC, Verification strategy at SoC level.
- Work with IP vendor and design partners to make sure coherency through the fabric, end to end latency, data flow, performance requirements are met.
- Track changes, progress on additional features required from IP vendor specific for SoC.
- Coach and mentor others in your areas of expertise
- Bachelor’s degree in electrical engineering, computer engineering, or equivalent.
- 8+ years of experience in ARM CPU based full chip SoC development.
- Experience with SoC subsystem and full chip development for a complex silicon project from concept to launch.
- Strong experience with using 3rd party Memory controllers and PHYs for (LP)DDR4, 5, 6 and HBM2,3,4.
- High proficiency in architecture analysis and performance modeling, ranging from simple analytical models to complex cycle accurate performance model and correlation, especially around fabric, system cache and memory controller
- Ability to leverage existing simulation capabilities (GEM5, FastSIM, Platform Architect) or create new simulation capabilities when necessary
- Detailed knowledge of ARM bus infrastructure (ACE/AXI/AHB), JEDEC standards
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