- Understand the system level use case
- Participate in the verification planning at all stages
- Testbench architecture and building or coding various part of the verification infrastructure which include test bench components, VIPs, drivers, checkers, and assertions
- Document and review the test plans, implement, and execute them
- Opportunities to do lab validation of the ASICs using Python
Contributions At a Group Level
- Support collecting various reusable verification components
- Support streamlining verification flows and processes
- Explore and adopt new verification methodologies
- UVM/System Verilog + Formal verification?
- SV UVM Experience
- Independently developed a testbench from scratch
- Experience of complete verification cycle in at least one project
Interested candidates share their resume at [email protected]
