SPI Protocol
The serial peripheral interface (SPI) is a communication interface used to send data between multiple devices. These devices are organized into a master and slave configuration, in which the master has control over the slaves and the slaves receive instruction from the master. The most common implementation of SPI consists of a configuration in which a single device is the master, and the remainder of the devices are slaves. SPI is a synchronous communication protocol that transmits and receives information simultaneously with high data transfer rates and is designed for board-level communication over short distances.
The SPI communication interface is advantageous when needing to communicate between multiple devices. It offers a higher data transfer rate than many other types of communication interfaces and allows for data to be sent and received at the same time.
4-wire SPI devices have four signals:
The device that generates the clock signal is called the main. Data transmitted between the main and the sub-node is synchronized to the clock generated by the main. SPI devices support much higher clock frequencies compared to I2C interfaces. Users should consult the product data sheet for the clock frequency specification of the SPI interface. SPI interfaces can have only one main and can have one or multiple sub-nodes. The chip select signal from the main is used to select the sub-node. This is normally an active low signal and is pulled high to disconnect the sub-node from the SPI bus. When multiple sub-nodes are used, an individual chip select signal for each sub-node is required from the main. In this article, the chip select signal is always an active low signal.
MOSI and MISO are the data lines. MOSI transmits data from the main to the sub-node and MISO transmits data from the sub-node to the main.
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Data Transmission
In SPI communication, the main must send the clock signal and select the sub-node by enabling the CS signal.?Usually chip select is an active low signal; hence, the main must send a logic 0 on this signal to select the subnode. SPI is a full-duplex interface; both the main and sub-node can send data simultaneously via the MOSI and MISO lines respectively. During SPI communication, the data is simultaneously transmitted (shifted out serially onto the MOSI/SDO bus) and received (the data on the bus (MISO/SDI) is sampled or read in). The serial clock edge synchronizes the shifting and sampling of the data. The SPI interface allows the user to select the rising or falling edge of the clock to sample and shift the data.
MOSI AND MISO SIGNALS
There are two data lines used in SPI communication known as MOSI and MISO. The MOSI signal sends data out from the master and is received by all slaves. Similarly, the MISO data line transmits data from one of the slave devices to the master device.
SLAVE SELECT SIGNAL
The slave select pin is utilized by the master to select which slave to communicate with. This line for the specific slave should be pulled low when the master wants to communicate with the slave. If multiple slave devices are used on the same bus, then each slave will have its own dedicated slave select line, while sharing the clock and data lines. When the master is finished communicating with the slave, the slave select line is pulled back high.
Clock Polarity and Clock Phase
In SPI, the main can select the clock polarity and clock phase. The CPOL bit sets the polarity of the clock signal during the idle state. The idle state is defined as the period when?CS?is high and transitioning to low at the start of the transmission and when?CS?is low and transitioning to high at the end of the transmission. The CPHA bit selects the clock phase. Depending on the CPHA bit, the rising or falling clock edge is used to sample and/or shift the data. The main must select the clock polarity and clock phase, as per the requirement of the sub-node. Depending on the CPOL and CPHA bit selection, four SPI modes are available.